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Method for packaging integrated circuit chips employing a polymer film overlay layer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B44C-001/20
출원번호 US-0240367 (1988-08-30)
발명자 / 주소
  • Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY) Welles
  • II Kenneth B. (Schenectady NY)
출원인 / 주소
  • General Electric Company (Schenectady NY 02)
인용정보 피인용 횟수 : 67  인용 특허 : 15

초록

A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale intergrated circuit chips. The system of the pr

대표청구항

A method for bonding a polymer film to a surface of at least one semiconductor chip device, said method comprising: (a) disposing said polymer film over said at least one chip device but not in substantial contact therewith; (b) applying vacuum conditions above and below said film so as to evacuate

이 특허에 인용된 특허 (15)

  1. Durand David (120 Lambie Cr. Portsmouth RI 02871), Apparatus for applying a dye image to a member.
  2. McGinty Joseph R. (Healdsburg CA) Donnelly Kevin A. (Huntsville AL), Apparatus for changing and repairing printed circuit boards.
  3. Hargis Billy M. (Hugo MN), Array of electronic packaging substrates.
  4. Hayakawa Masao (Kyoto JPX) Maeda Takamichi (Yamatokoriyama JPX) Kumura Masao (Nara JPX), Flat shaped semiconductor encapsulation.
  5. Miniet Jay J. (Ft. Lauderdale FL), Flexible printed circuit board having integrated circuit die or the like affixed thereto.
  6. Johnston Orin B. (5548 W. 78th St. Minneapolis MN 55435), Heat bonding device.
  7. Deroode Jean R. (Lesigny FRX), Method of and apparatus for decorating substrates.
  8. Hoge Carl E. (Encinitas CA) Lin Gregory K. (San Diego CA), Method of attaching a protective film to an integrated circuit.
  9. Becker Charles A. (Rexford NY), Method of fabricating high density electronic circuits having very narrow conductors.
  10. Walter William J. (Algonac MI), Method of forming a contoured laminate.
  11. Takeda Shiro (Sagamihara JPX) Nakajima Minoru (Kawasaki JPX), Method of manufacturing electronic device having multilayer wiring structure.
  12. Ng Kwok K. (Union NJ) Sze Simon M. (Berkeley Heights NJ), Packaging microminiature devices.
  13. Cole ; Jr. Herbert S. (Scotia NY) Liu Yung S. (Scotia NY) Philipp Herbert R. (Scotia NY), Process for removing organic material in a patterned manner from an organic film.
  14. Fitzer, Robert C.; Deyak, Frank L.; Fabbrini, Charles J., Transfer sheet bearing a thermally transferable ink composition and article made therefrom.
  15. Mizuno Shogo (Toride JPX) Suzuki Takao (Kawagoe JPX) Kawasaki Sadanobu (Tokyo JPX) Takeda Hideichiro (Tokyo JPX), Transfer sheet with resist portions.

이 특허를 인용한 특허 (67)

  1. Robert John Wojnarowski ; Glenn Alan Forman ; Yung Sheng Liu, Alignment of optical interfaces for data communication.
  2. Wojnarowski Robert John ; Forman Glenn Alan ; Liu Yung Sheng, Alignment of optical interfaces for data communication.
  3. Saia Richard Joseph ; Durocher Kevin Matthew ; Rose James Wilson, Amorphous hydrogenated carbon hermetic structure and fabrication method.
  4. Miyano,Junichi; Toshikawa,Kiyohiko; Motoyama,Yoshikazu, Apparatus and method for manufacturing semiconductor.
  5. Saia, Richard Joseph; Durocher, Kevin Matthew; Rose, James Wilson; Douglas, Leonard Richard, Apparatus for aligning die to interconnect metal on flex substrate.
  6. Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Apparatus for circuit encapsulation.
  7. Brand J. Michael, Apparatus for filling a gap between spaced layers of a semiconductor.
  8. Brand J. Michael, Apparatus for filling a gap between spaced layers of a semiconductor.
  9. Brand, J. Michael, Apparatus for filling a gap between spaced layers of a semiconductor.
  10. J. Michael Brand, Apparatus for filling a gap between spaced layers of a semiconductor.
  11. Fillion Raymond Albert ; Burdick ; Jr. William Edward, Chip burn-in and test structure and method.
  12. Fillion Raymond Albert ; Burdick ; Jr. William Edward, Chip burn-in and test structure and method.
  13. Oppermann Hans-Hermann,DEX ; Zakel Elke,DEX ; Azdasht Ghassem,DEX ; Kasulke Paul,DEX, Chip module with conductor paths on the chip bonding side of a chip carrier.
  14. Fillion Raymond Albert ; Balch Ernest Wayne ; Kolc Ronald Frank ; Burdick ; Jr. William Edward ; Wojnarowski Robert John ; Douglas Leonard Richard ; Gorczyca Thomas Bert, Circuit chip package and fabrication method.
  15. Raymond Albert Fillion ; Ernest Wayne Balch ; Ronald Frank Kolc ; William Edward Burdick, Jr. ; Robert John Wojnarowski ; Leonard Richard Douglas ; Thomas Bert Gorczyca, Circuit chip package and fabrication method.
  16. John R. Saxelby, Jr. ; Walter R. Hedlund, III, Circuit encapsulation.
  17. Saxelby, Jr., John R.; Hedlund, III, Walter R., Circuit encapsulation.
  18. Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Circuit encapsulation process.
  19. Woychik, Charles Gerard; Fillion, Raymond Albert, Demountable interconnect structure.
  20. Shaddock, David Mulford, Dual encapsulation for an LED.
  21. Wojnarowski Robert John, Electronic device pad relocation, precision placement, and packaging in arrays.
  22. Wojnarowski Robert John, Electronic device pad relocation, precision placement, and packaging in arrays.
  23. Burdick, Jr.,William Edward; Rose,James Wilson; Tkaczyk,John Eric; Meirav,Oded; Arenson,Jerome Stephen; Hoffman,David Michael, Electronic packaging and method of making the same.
  24. Wojnarowski Robert J. (Ballston Lake NY) Gorczyca Thomas B. (Schenectady NY), Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers.
  25. Wojnarowski Robert John (Ballston Lake NY) Gorczyca Thomas Bert (Schenectady NY), Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers.
  26. Shinjo, Yoshiaki; Shimobeppu, Yuzo; Teshirogi, Kazuo; Yoshimoto, Kazuhiro, Film bonding method, film bonding apparatus, and semiconductor device manufacturing method.
  27. DeMeter, Edward C.; Powell, R. Michael, Fixture and method of holding and debonding a workpiece with the fixture.
  28. Saia Richard Joseph ; Durocher Kevin Matthew ; Cole Herbert Stanley, Flexible interconnect film including resistor and capacitor layers.
  29. Fillion, Raymond Albert; Durocher, Kevin Matthew; Saia, Richard Joseph; Woychik, Charles Gerard, Interconnect structure.
  30. Wickramanayaka, Sunil, Method and apparatus for chip-to-wafer integration.
  31. Brand J. Michael, Method and apparatus for filling a gap between spaced layers of a semiconductor.
  32. J. Michael Brand, Method and apparatus for filling a gap between spaced layers of a semiconductor.
  33. Richard Joseph Saia ; Kevin Matthew Durocher ; James Wilson Rose ; Leonard Richard Douglas, Method for aligning die to interconnect metal on flex substrate.
  34. Saia Richard Joseph ; Durocher Kevin Matthew ; Cole Herbert Stanley, Method for fabricating a flexible interconnect film with resistor and capacitor layers.
  35. Saia Richard Joseph (Schenectady NY) Gorowitz Bernard (Clifton Park NY) Durocher Kevin Matthew (Waterford NY), Method for fabricating a stack of two dimensional circuit modules.
  36. Pogge H. Bernhard ; Davari Bijan ; Greschner Johann,DEX ; Kalter Howard L., Method for fabricating a very dense chip package.
  37. Brand, J. Michael, Method for filling a gap between spaced layers of a semiconductor.
  38. Bayerer, Reinhold; Hohlfeld, Olaf, Method for producing a composite and a power semiconductor module.
  39. Tyan, Yuan-Sheng; Farruggia, Giuseppe; Vazan, Fridrich; Cushman, Thomas R., Method for transferring of organic material from a donor to form a layer in an OLED device.
  40. Pogge, H. Bernhard; Prasad, Chandrika; Yu, Roy, Method of fabricating integrated electronic chip with an interconnect device.
  41. Woychik, Charles Gerard; Fillion, Raymond Albert, Method of making demountable interconnect structure.
  42. Chua,Swee Kwang; Low,Siu Waf; Chia,Yong Poo; Eng,Meow Koon; Neo,Yong Loo; Boon,Suan Jeung; Huang,Suangwu; Zhou,Wei, Method of making multichip wafer level packages and computing systems incorporating same.
  43. De Vita, Vincenzo; D'Agostino, Claudio; Lauriola, Matteo; Cuciniello, Ciro, Method of manufacturing a Z-section component from composite material.
  44. Narasimhan, Swaminathan; Bessho, Koji, Methods and systems for controlling data acquisition system noise.
  45. Onishi Hisatomo (Tokyo JPX), Photoforming method and apparatus.
  46. Durocher, Kevin Matthew; Balch, Ernest Wayne; Krishnamurthy, Vikram B.; Saia, Richard Joseph; Cole, Herbert Stanley; Kolc, Ronald Frank, Plastic packaging of LED arrays.
  47. Durocher, Kevin Matthew; Balch, Ernest Wayne; Krishnamurthy, Vikram B.; Saia, Richard Joseph; Cole, Herbert Stanley; Kolc, Ronald Frank, Plastic packaging of LED arrays.
  48. Durocher, Kevin Matthew; Balch, Ernest Wayne; Krishnamurthy, Vikram B.; Saia, Richard Joseph; Cole, Herbert Stanley; Kolc, Ronald Frank, Plastic packaging of LED arrays.
  49. H. Bernhard Pogge ; Chandrika Prasad ; Roy Yu, Process for making fine pitch connections between devices and structure made by the process.
  50. Pogge, H. Bernhard; Prasad, Chandrika; Yu, Roy, Process for making fine pitch connections between devices and structure made by the process.
  51. Pogge,H. Bernhard; Prasad,Chandrika; Yu,Roy, Process for making fine pitch connections between devices and structure made by the process.
  52. Pogge H. Bernhard ; Iyer Subramania S., Process for precise multichip integration and product thereof.
  53. Pogge H. Bernhard, Process for precision alignment of chips for mounting on a substrate.
  54. William Tze-You Chen ; Michael Anthony Gaynes ; Eric Arthur Johnson ; Tien Yue Wu, Protective cover plate for flip chip assembly backside.
  55. Wojnarowski Robert John, Semiconductor interconnect structure for high temperature applications.
  56. Wojnarowski Robert John, Semiconductor interconnect structure for high temperature applications.
  57. Eichelberger Charles William, Single chip modules, repairable multichip modules, and methods of fabrication thereof.
  58. Taskar,Nikhil Ramesh; Krishnamurthy,Vikram Bidare, Solid state lighting device with reduced form factor including LED with directional emission and package with microoptics.
  59. Liu Yung Sheng, Structure and fabrication method for interconnecting light emitting diodes with metallization extending through vias in.
  60. Pogge H. Bernhard ; Iyer Subramania S., Structure for precision multichip assembly.
  61. Bedzyk, Mark D., Tensioning unrolled donor substrate to facilitate transfer of organic material.
  62. Ueyama,Tsutomu; Iseki,Izuru; Sato,Norio; Machida,Katsuyuki; Kyuragi,Hakaru, Thin film forming apparatus and thin film forming method.
  63. Pogge H. Bernhard ; Davari Bijan ; Greschner Johann,DEX ; Kalter Howard L., Very dense chip package.
  64. Pogge H. Bernhard ; Greschner Johann,DEX ; Kalter Howard Leo ; Rosner Raymond James, Very dense integrated circuit package.
  65. Pogge H. Bernhard ; Greschner Johann,DEX ; Kalter Howard Leo ; Rosner Raymond James, Very dense integrated circuit package and method for forming the same.
  66. Pogge H. Bernhard, Wafer thickness compensation for interchip planarity.
  67. Pogge, H. Bernhard, Wafer thickness compensation for interchip planarity.
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