$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

High performance interconnect system for an integrated circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/28
  • H01L-027/02
출원번호 US-0393826 (1989-08-14)
발명자 / 주소
  • Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA)
출원인 / 주소
  • Fairchild Semiconductor Corporation (Cupertino CA 02)
인용정보 피인용 횟수 : 149  인용 특허 : 15

초록

A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is

대표청구항

A semiconductor integrated circuit device including an interconnect structure for electrically connecting regions in a semiconductor substrate, said interconnect structure comprising: a plurality of interconnects, each interconnect being structurally separated from other interconnects except at elec

이 특허에 인용된 특허 (15)

  1. Kern ; Werner ; Tracy ; Chester Edwin, Combination glass/low temperature deposited Si.sub.w N.sub.x H.sub.y O.sub. z.
  2. Fischer Franz (Munich DEX), Integrated semiconductor circuits with contact interconnect levels comprised of an aluminum/silicon alloy.
  3. Itsumi Manabu (Hoya JPX) Ehara Kohei (Kodaira JPX) Muramoto Susumu (Hachioji JPX) Matsuo Seitaro (Hachioji JPX), Manufacturing process for semiconductor integrated circuits.
  4. Mercier Jacques S. (Kanata CAX) Ho Vu Q. (Ottawa CAX), Method for improving step coverage of dielectrics in VLSI circuits.
  5. Hartmann Jol (Claix FRX) Jeuch Pierre (Seyssins FRX), Method for interconnecting the active zones and/or the gates of a C/MOS integrated circuit.
  6. Allen Donald E. (Gilbert AZ) Gross Richard A. (Tempe AZ) Knuth Howard D. (Tempe AZ), Method of fabricating air supported crossovers.
  7. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY), Multichip integrated circuit packaging configuration and method.
  8. Maddocks Fred Sterns (Poughkeepsie NY), Planar insulation of conductive patterns by chemical vapor deposition and sputtering.
  9. Wu Andrew L. (Shrewsbury MA), Planar interconnect for integrated circuits.
  10. Balasubramanyam Karanam (Hopewell Junction NY) Dally Anthony J. (Pleasant Valley NY) Riseman Jacob (Poughkeepsie NY) Ogura Seiki (Hopewell Junction NY), Process for forming planar chip-level wiring.
  11. Pammer Erich (Taufkirchen DEX), Semiconductor component comprising bump-like, metallic lead contacts and multilayer wiring.
  12. Sasaki Nobuo (Kawasaki JPX), Semiconductor device having new conductive interconnection structure and method for manufacturing the same.
  13. Higashi Akio (Kanagawa JPX) Shinada Haruji (Kanagawa JPX) Kawajiri Kazuhiro (Kanagawa JPX) Ono Yoshihiro (Kanagawa JPX) Saitou Mitsuo (Kanagawa JPX) Tamura Hiroshi (Kanagawa JPX) Ikeda Mitsuru (Kanag, Solid state imaging device and process for fabricating the same.
  14. Yorikane, Masaharu; Ohseki, Noboru, Titanium coated aluminum leads.
  15. Barry Vincent J. (Tempe AZ) Boucher-Puputti Brenda A. (Mesa AZ) Fitzgerald Thomas W. (Scottsdale AZ) Bawolek Edward J. (Chandler AZ), Via formation for multilayered metalization.

이 특허를 인용한 특허 (149)

  1. Liu Chwen-Ming,TWX, Abatement of electron beam charging distortion during dimensional measurements of integrated circuit patterns with scan.
  2. Burak, Dariusz; Choy, John; Grannen, Kevin J.; Zou, Qiang, Acoustic resonator comprising collar and acoustic reflector with temperature compensating layer.
  3. Burak, Dariusz; Choy, John; Shirakawa, Alexandre; Nikkel, Phil, Acoustic resonator comprising collar and frame.
  4. Burak, Dariusz; Shirakawa, Alexandre; Choy, John; Nikkel, Phil, Acoustic resonator having collar structure.
  5. Nikkel, Phil; Feng, Chris; Burak, Dariusz; Choy, John, Acoustic resonator having guard ring.
  6. Lien Chuen-Der ; Lee Shih-Ked ; Yen Chu-Tsao, Air gap with borderless contact.
  7. Hisaka Takayuki (Itami JPX), Airbridge wiring structure for MMIC.
  8. Yeh Kuantai ; Chatila Ahmad ; Sharifzadeh Shahin, Alignment process compatible with chemical mechanical polishing.
  9. Akram, Salman; Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection.
  10. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  11. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  12. Woo, Christy Mei-Chu; Wang, Pin-Chin Connie; Bernard, Joffre F., Barrier-to-seed layer alloying in integrated circuit interconnects.
  13. Burak, Dariusz; Grannen, Kevin J.; Larson, III, John D.; Shirakawa, Alexandre, Bulk acoustic resonator comprising piezoelectric layer and inverse piezoelectric layer.
  14. Husher, John Durbin, Buried power bus utilized as a sinker for high current, high power semiconductor devices and a method for providing the same.
  15. Husher, John Durbin, Buried power buss utilized as a ground strap for high current, high power semiconductor devices and a method for providing the same.
  16. Husher,John Durbin, Buried power buss utilized as a ground strap for high current, high power semiconductor devices and a method for providing the same.
  17. Forbes, Leonard, Capacitive techniques to reduce noise in high speed interconnections.
  18. Forbes,Leonard, Capacitive techniques to reduce noise in high speed interconnections.
  19. Farrar,Paul A., Coating of copper and silver air bridge structures to improve electromigration resistance and other applications.
  20. Farrar,Paul A., Coating of copper and silver air bridge structures to improve electromigration resistance and other applications.
  21. Farrar,Paul A., Coating of copper and silver air bridge structures to improve electromigration resistance and other applications.
  22. Farrar,Paul A., Coating of copper and silver air bridge structures to improve electromigration resistance and other applications.
  23. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Coaxial integrated circuitry interconnect lines, and integrated circuitry.
  24. Claude Louis Bertin ; Gordon Arthur Kelley ; Dennis Arthur Schmidt ; William Robert Tonti ; Jerzy Maria Zalesinski, Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality.
  25. Pluymers Brian Alan ; Teti Richard Joseph, Compliant RF coaxial interconnect.
  26. Ahn Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  27. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  28. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  29. Forbes, Leonard; Ahn, Kie Y., Current mode signal interconnects and CMOS amplifier.
  30. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  31. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  32. Rodgers T. J. ; Geha Sam ; Petti Chris ; Yen Ting-Pwu, Edge metal for interconnect layers.
  33. Filippi, Ronald G.; Fitzsimmons, John A.; Kolvenbach, Kevin; Wang, Ping-Chuan, Electromigration immune through-substrate vias.
  34. Yang, Xiaomin; Eckert, Andrew Robert, Electron beam lithography method for plating sub-100 nm trenches.
  35. Ahn,Kie Y.; Forbes,Leonard, Electronic apparatus with deposited dielectric layers.
  36. Brian Alan Pluymers ; Doreen Marie Nixon, Fabrication of a circuit module with a coaxial transmission line.
  37. Pluymers Brian Alan ; Nixon Doreen Marie, Fabrication of a circuit module with a coaxial transmission line.
  38. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
  39. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
  40. Tanimoto,Satoshi, Heat resistant ohmic electrode and method of manufacturing the same.
  41. Tanimoto,Satoshi, Heat resistant ohmic electrode and method of manufacturing the same.
  42. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  43. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  44. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  45. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  46. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  47. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  48. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability composite films to reduce noise in high speed interconnects.
  49. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability composite films to reduce noise in high speed interconnects.
  50. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability composite films to reduce noise in high speed interconnects.
  51. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability layered films to reduce noise in high speed interconnects.
  52. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.
  53. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.
  54. Akram,Salman; Ahn,Kie Y.; Forbes,Leonard, High permeability layered magnetic films to reduce noise in high speed interconnection.
  55. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  56. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  57. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  58. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  59. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability thin films and patterned thin films to reduce noise in high speed interconnections.
  60. Geha, Sam G., Hot metallization process.
  61. Harvey Ian, Integrated circuit device interconnection techniques.
  62. Manning,Monte, Integrated circuitry and a semiconductor processing method of forming a series of conductive lines.
  63. Manning,Monte, Integrated circuitry and a semiconductor processing method of forming a series of conductive lines.
  64. Ahn Kie Y., Integrated circuitry and methods of forming integrated circuitry.
  65. Manning, Monte, Integrated circuitry conductive lines.
  66. Kie Y. Ahn, Integrated circuitry having conductive passageway interconnecting circuitry on front and back surfaces of a wafer fragment.
  67. Jeong, Yong-sang, Integrated circuits having plugs in conductive layers therein and related methods.
  68. Husher,John Durbin, Integrated device technology using a buried power buss for major device and circuit advantages.
  69. Lee, Cheng-Shih; Chang, Edward Yi; Chang, Huang-Choung, Interconnect of group III-V semiconductor device and fabrication method for making the same.
  70. Minh Van Ngo ; Christy Mei-Chu Woo, Low dielectric constant stop layer for integrated circuit interconnects.
  71. Nakagawa,Kanae, Manufacturing method of wiring substrate.
  72. Lien Chuen-Der ; Lee Shih-Ked ; Yen Chu-Tsao, Method for fabricating air gap with borderless contact.
  73. Weatherspoon, Michael Raymond; Rendek, Jr., Louis Joseph; Shacklette, Lawrence Wayne; Maloney, Robert Patrick; Smith, David M., Method for making electrical structure with air dielectric and related electrical structures.
  74. Weatherspoon, Michael Raymond; Rendek, Jr., Louis Joseph; Shacklette, Lawrence Wayne; Maloney, Robert Patrick; Smith, David M., Method for making electrical structure with air dielectric and related electrical structures.
  75. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
  76. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Method for making multilayered coaxial interconnect structure.
  77. Sekiguchi Mitsuru,JPX, Method for making semiconductor device containing low carbon film for interconnect structures.
  78. Levinson Harry J. ; Bell Scott A. ; Lyons Christopher F. ; Nguyen Khanh B. ; Wang Fei ; Yang Chih Yuh, Method for transferring patterns created by lithography.
  79. Larson, III, John; Mishin, Sergey, Method of fabricating piezoelectric material with selected c-axis orientation.
  80. Dalal, Hormazdyar M.; Prasad, Jagdish, Method of forming a shielded semiconductor device and structure therefor.
  81. Tuttle Mark E. (Boise ID), Method of forming battery terminal housing members and battery terminal housing member sheets.
  82. Yen Ting, Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit.
  83. Hasegawa Makiko,JPX ; Toyoda Yoshihiko,JPX ; Mori Takeshi,JPX ; Fukada Tetsuo,JPX, Method of making embedded wiring system.
  84. Blosse, Alain; Thedki, Sanjay; Qiao, Jianmin; Gilboa, Yitzhak, Method of making metallization and contact structures in an integrated circuit.
  85. Alain Blosse ; Sanjay Thedki ; Jianmin Qiao ; Yitzhak Gilboa, Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer.
  86. Lin Shih-Chi,TWX ; Chen Yen-Ming,TWX ; Chang Juin-Jie,TWX ; Huang Kuei-Wu,TWX, Method of manufacturing air gap in multilevel interconnection.
  87. Akram, Salman; Meikle, Scott G., Method of using tantalum-aluminum-nitrogen material as diffusion barrier and adhesion layer in semiconductor devices.
  88. Salman Akram ; Scott G. Meikle, Method of using tantalum-aluminum-nitrogen material as diffusion barrier and adhesion layer in semiconductor devices.
  89. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  90. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  91. Ahn, Kie Y.; Forbes, Leonard, Methods for atomic-layer deposition.
  92. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  93. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  94. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  95. Tuttle Mark E. (Boise ID), Methods of forming a button-type battery terminal housing member sheet and of forming button-type batteries.
  96. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Methods of forming coaxial integrated circuitry interconnect lines.
  97. Manning Monte, Methods of forming conductive lines.
  98. Pluymers Brian Alan ; Nixon Doreen Marie ; Teti Richard Joseph ; Hayes Robert Edward, Multi-circuit RF connections using molded and compliant RF coaxial interconnects.
  99. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
  100. Hasegawa Makiko,JPX ; Toyoda Yoshihiko,JPX ; Mori Takeshi,JPX ; Fukada Tetsuo,JPX, Multilevel embedded wiring system.
  101. Ahn, Kie Y.; Forbes, Leonard, Multilevel interconnect structure with low-k dielectric.
  102. Ahn,Kie Y.; Forbes,Leonard, Multilevel interconnect structure with low-k dielectric.
  103. Siniaguine, Oleg; Savastiouk, Sergey, Packaging of integrated circuits and vertical integration.
  104. Jamneala, Tiberiu; Ruby, Richard C., Piezoelectric resonator structures and electrical filters having frame elements.
  105. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  106. Abe,Kazuhide, Production method for wiring structure of semiconductor device.
  107. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
  108. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
  109. Whitlock John Perry ; Corrigan ; III George H., Segmented electrical distribution plane.
  110. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
  111. Sekiguchi, Mitsuru, Semiconductor device and method for fabricating the same.
  112. Komukai, Toshiaki; Harakawa, Hideaki, Semiconductor device comprising transistor and capacitor and method of manufacturing the same.
  113. Kono Takahiro,JPX, Semiconductor device having A1 alloy wiring.
  114. Whetten, Timothy J.; Richling, Wayne P., Semiconductor device having an airbridge and method of fabricating the same.
  115. Whetten, Timothy J.; Richling, Wayne P., Semiconductor device having an airbridge and method of fabricating the same.
  116. Watanabe, Kenichi, Semiconductor device manufacturing method capable of reliable inspection for hole opening and semiconductor devices manufactured by method.
  117. Watanabe,Kenichi, Semiconductor device manufacturing method capable of reliable inspection for hole opening and semiconductor devices manufactured by method.
  118. Watanabe, Kenichi, Semiconductor device manufacturing method capable of reliable inspection for hole opening and semiconductor devices manufactured by the method.
  119. Nicholls, Howard Charles; Norrington, Michael John; Thompson, Michael Kevin, Semiconductor devices and fabrication thereof.
  120. Park, O Seo; Kim, Sun-Oo; Herold, Klaus, Semiconductor devices and methods of manufacturing thereof.
  121. Liu, Yong; Zhang, Jiangyuan; Qian, Qiuxiao, Semiconductor die package including IC driver and bridge.
  122. Lien, Chuen-Der; Lee, S. K., Semiconductor integrated circuit with an insulation structure having reduced permittivity.
  123. Shekhar Pramanick ; Takeshi Nogami, Semiconductor interconnect barrier and manufacturing method thereof.
  124. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, Semiconductor memory device with high permeability composite films to reduce noise in high speed interconnects.
  125. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, Semiconductor memory device with high permeability lines interposed between adjacent transmission lines.
  126. Lichter, Gerd, Semiconductor structure having an interconnect and method of producing the semiconductor structure.
  127. Dalal, Hormazdyar M.; Prasad, Jagdish, Shielded semiconductor device structure.
  128. Farrar, Paul A., Structures and methods to enhance copper metallization.
  129. Farrar, Paul A., Structures and methods to enhance copper metallization.
  130. Farrar,Paul A., Structures and methods to enhance copper metallization.
  131. Farrar,Paul A., Structures and methods to enhance copper metallization.
  132. Salman Akram ; Scott G. Meikle, Tantalum - aluminum - nitrogen material for semiconductor devices.
  133. Akram Salman ; Meikle Scott G., Tantalum-aluminum-nitrogen material for semiconductor devices.
  134. Akram Salman ; Meikle Scott G., Tantalum-aluminum-nitrogen material for semiconductor devices.
  135. Akram, Salman; Meikle, Scott G., Tantalum-aluminum-nitrogen material for semiconductor devices.
  136. Chanda, Kaushik; Filippi, Ronald G.; Wang, Ping Chuan, Test structure for electromigration analysis and related method.
  137. Chanda, Kaushik; Filippi, Ronald G.; Wang, Ping-Chuan, Test structure for electromigration analysis and related method.
  138. Iyer, Ravi, Titanium boride gate electrode and interconnect.
  139. Iyer, Ravi, Titanium boride gate electrode and interconnect.
  140. Iyer Ravi, Titanium boride gate electrode and interconnect and methods regarding same.
  141. Iyer, Ravi, Titanium boride gate electrode and interconnect and methods regarding same.
  142. Iyer,Ravi, Titanium silicide boride gate electrode.
  143. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  144. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  145. Forbes,Leonard; Cloud,Eugene H.; Ahn,Kie Y., Transmission lines for CMOS integrated circuits.
  146. Leonard Forbes ; Eugene H. Cloud ; Kie Y. Ahn, Transmission lines for CMOS integrated circuits.
  147. Moslehi Mehrdad M., Ultra high-speed chip interconnect using free-space dielectrics.
  148. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
  149. Abe, Kazuhide, Wiring structure of semiconductor device and production method of the device.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로