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특허 상세정보

Dual read/write register file memory

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G11C-007/00   
미국특허분류(USC) 365/23005 ; 365/18904 ; 365/23002
출원번호 US-0286552 (1988-12-19)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 16  인용 특허 : 3
초록

A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single write port RAM. Additionally, the register file includes a plurality of clocked input registers arranged in pairs for storing command, address and data signals for two write ports. The different pairs of registers are connected as inputs to a first set of multip...

대표
청구항

A dual port read/write memory having a single write input sort comprising: a random access memory (RAM) array having a plurality of addressable storage locations, said RAM having said single write port including a set of write data, address and write enable input terminals; clocked input register means for storing sets of write data, address and command information associated with a pair of ports; multiplexer selector means connected to said register means for receiving said sets of information and said multiplexer selector means being connected to apply...

이 특허를 인용한 특허 피인용횟수: 16

  1. Chu, Sam Gat-Shang; Delaney, Maureen Anne; Islam, Saiful; Nguyen, Dung Quoc; Nahidi, Jafar. Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array. USP2010027663963.
  2. Aranda, Michael A.. Categorized pixel variable buffering and processing for a graphics system. USP1994065321809.
  3. Neil P. Raftery GB; Mathew R. Arcoleo. Circuit architecture and method of writing data to a memory. USP2002036360307.
  4. Cherukuri Ravikrishna V. ; Rozario Ranjit J.. Computer system including system controller with a write buffer and plural read buffers for decoupled busses. USP1998045745732.
  5. Yadav, Rishi; Refalo, Alan. Deterministic collision detection. USP2011067962698.
  6. Chu,Sam Gat Shang; Delaney,Maureen Anne; Islam,Saiful; Nguyen,Dung Quoc; Nahidi,Jafar. Method for providing multiple reads/writes using a 2read/2write register file array. USP2008077400548.
  7. Martell Robert W. ; Henstrom Alexander P.. Multi-port register file for a reservation station including a pair of interleaved storage cells with shared write data. USP1998095813037.
  8. Damodaran, Raguram; Vankatasubramanian, Ramakrishnan; Bhoria, Naveen. Multi-port register file with an input pipelined architecture and asynchronous read data forwarding. USP2014108862835.
  9. Damodaran, Raguram; Venkatasubramanian, Ramakrishnan; Bhoria, Naveen. Multi-port register file with an input pipelined architecture with asynchronous reads and localized feedback. USP2014108862836.
  10. Butcher Lawrence L.. Pipelining to improve the interface of memory devices. USP1999115987578.
  11. Tran Thang M.. Register file having multiple register storages for storing data from multiple data streams. USP1998015713039.
  12. Payne Robert L.. Scalable N-port memory structures. USP1999075923608.
  13. Jang Seong Jun,KRX. Synchronous memory device having dual input registers of pipeline structure in data path. USP1998085796675.
  14. Crary Philip D.. System and method for simultaneously reading and writing data in a random access memory. USP1998095802579.
  15. Tsubone, Kenji. Vehicle heat pump with a selective heat storing element and two circulation loops. USP2012078220284.
  16. Lin, Kenneth Chenghao; Zhang, Bingchun. Wide bandwidth read and write memory system and method. USP2016039299448.