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Semi-conductor integrated circuits/systems 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/173
출원번호 US-0905777 (1986-09-10)
우선권정보 GB-0022534 (1985-09-11); GB-0026143 (1985-10-23); GB-0017705 (1986-07-19)
발명자 / 주소
  • Austin Kenneth (Northwich GBX)
출원인 / 주소
  • Pilkington Micro-Electronics Limited (Merseyside GB2 03)
인용정보 피인용 횟수 : 153  인용 특허 : 12

초록

Configurable semiconductor integrated circuits as-made each have a plurality of logic circuits formed at discrete sites. For each logic circuit, direct selectably conducting/non-conducting connection paths extend from its output to input of a first set of other logic circuits and to its inputs from

대표청구항

A configurable semiconductor integrated circuit which, as-made, comprises an area thereof formed with a plurality of logic circuits at discrete sites, respectively, wherein each said logic circuit is only capable of performing a simple logic function, and wherein each said logic circuit comprises at

이 특허에 인용된 특허 (12)

  1. Kant Rajni (Milpitas CA) Chen Kun-Nau (San Jose CA), Configurable logic gate array.
  2. Moore, Donald W.; Verstraete, Rick A., Functionally redundant logic network architectures.
  3. Wyland David C. (San Jose CA), Integrated circuit component.
  4. Kraft Wayne R. (Coral Springs FL) Cases Moises (Delray Beach FL) Stahl ; Jr. William L. (Coral Springs FL) Thoma Nandor G. (Boca Raton FL) Wyatt Virgil D. (Lighthouse Point FL), Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus.
  5. Tsui Cyrus (San Jose CA) Chan Andrew K. L. (Milpitas CA) Chan Albert (San Jose CA) Fitzpatrick Mark E. (San Jose CA) Ansari Zahid (Sunnyvale CA), Output circuit for a programmable logic array.
  6. Wheeler Glenn (Dallas TX) Ptasinski James F. (Dallas TX), Programmable architecture logic.
  7. Wong, Sing Y.; Birkner, John M., Programmable array logic circuit with shared product terms.
  8. Furtek Frederick C. (Arlington MA), Programmable, asynchronous logic cell and array.
  9. Cox Dennis T. (Kingston NY) Devine William T. (Ulster Park NY) Kelly Gilbert J. (Red Hook NY), Segmented parallel rail paths for input/output signals.
  10. Tanizawa Tetsu (Kawasaki JPX) Omichi Hitoshi (Kawasaki JPX) Mitono Yoshiharu (Tokyo JPX), Semiconductor gate array device having an improved interconnection structure.
  11. Carter William S. (Santa Clara CA), Special interconnect for configurable logic array.
  12. Malcolm Robert B. (Scottsdale AZ) McDaniel Clarence E. (Wichita Falls TX), Standardized digital logic chip.

이 특허를 인용한 특허 (153)

  1. Smith, Michael John Sebastian; Rosenband, Daniel L.; Wang, David T.; Rajan, Suresh Natarajan, Adjusting the timing of signals associated with a memory system.
  2. Smith, Michael John; Rosenband, Daniel L.; Wang, David T.; Rajan, Suresh Natarajan, Adjusting the timing of signals associated with a memory system.
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  27. Kean Thomas A.,GBX, Configurable cellular array.
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  31. Rajan, Suresh Natarajan; Wang, David T., Configurable memory system with interface circuit.
  32. Rajan, Suresh Natarajan; Wang, David T., Configurable multirank memory system with interface circuit.
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  34. Sharon Sheau-Pyng Lin ; Ping-Sheng Tseng, Converification system and method.
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  36. Ting,Benjamin S.; Pani,Peter M., Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric.
  37. Zohni, Wael O.; Schmidt, William L.; Smith, Michael John Sebastian; Plunkett, Jeremy Matthew, Embossed heat spreader.
  38. Zohni, Wael O.; Schmidt, William; Smith, Michael J. S.; Plunkett, Jeremy Matthew, Embossed heat spreader.
  39. Smith, Michael John Sebastian; Rajan, Suresh Natarajan; Wang, David T, Emulation of abstracted DIMMS using abstracted DRAMS.
  40. Smith, Michael J. S.; Rajan, Suresh Natarajan; Wang, David T., Emulation of abstracted DIMMs using abstracted DRAMs.
  41. Bershteyn, Mikhail; Seeley, Stephen Frederick, Emulation system for verifying a network device.
  42. Bershteyn, Mikhail; Poplack, Mitchell G.; Salitrennik, Viktor, Emulation system with improved reliability of interconnect and a method for programming such interconnect.
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  45. Ting, Benjamin S.; Pani, Peter M., Enhanced permutable switching network with multicasting signals for interconnection fabric.
  46. Ting, Benjamin S.; Pani, Peter M., Enhanced permutable switching network with multicasting signals for interconnection fabric.
  47. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA logic cell internal structure including pair of look-up tables.
  48. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector clock lines.
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  61. Rosenband, Daniel L.; Weber, Frederick Daniel; Smith, Michael John Sebastian, Hybrid memory module.
  62. Rosenband, Daniel L.; Weber, Frederick Daniel; Smith, Michael John Sebastian, Hybrid memory module.
  63. Rajan, Suresh N., Integrated memory core and memory interface circuit.
  64. Pani,Peter M.; Ting,Benjamin S., Interconnection fabric using switching networks in hierarchy.
  65. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits.
  66. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit.
  67. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for performing power saving operations during a command-related latency.
  68. Poplevine, Pavel; Lin, Hengyang; Franklin, Andrew J., Low power static RAM architecture.
  69. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory apparatus operable to perform a power-saving operation.
  70. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory apparatus operable to perform a power-saving operation.
  71. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit simulation system and method with refresh capabilities.
  72. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit simulation with power saving capabilities.
  73. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
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  75. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
  76. Park, Chul-woo; Jun, Young-hyun; Choi, Joo-sun; Hwang, Hong-sun, Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same.
  77. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory device with emulated characteristics.
  78. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael J. S.; Wang, David T.; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilites.
  79. Rajan, Suresh N.; Schakel, Keith R; Smith, Michael J. S.; Wang, David T; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilities.
  80. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael J. S.; Wang, David T.; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilities.
  81. Smith, Michael John Sebastian; Rajan, Suresh Natarajan, Memory modules with reliability and serviceability functions.
  82. Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory refresh apparatus and method.
  83. Lin Sharon Sheau-Pyng ; Tseng Ping-Sheng, Memory simulation system and method.
  84. Wang, David T.; Rajan, Suresh Natarajan, Memory system for synchronous data transmission.
  85. Smith, Michael J. S.; Rajan, Suresh Natarajan, Memory systems and memory modules.
  86. Smith, Michael John Sebastian; Rajan, Suresh Natarajan, Memory systems and memory modules.
  87. Kuijsten Han, Method and apparatus for a trace buffer in an emulation system.
  88. Chen Tao Shinn ; Bui Dam Van, Method and apparatus for configurable memory emulation.
  89. Sample Stephen P. ; Bershteyn Mikhail, Method and apparatus for design verification using emulation and simulation.
  90. Huang Thomas B., Method and apparatus for emulating multi-ported memory circuits.
  91. Pani Peter M. ; Ting Benjamin S., Method and apparatus for universal program controlled bus.
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  93. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  95. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  97. Pani,Peter M.; Ting,Benjamin S., Method and apparatus for universal program controlled bus architecture.
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  99. Butts, Michael R.; Batcheller, Jon A., Method of using electronically reconfigurable logic circuits.
  100. Rajan, Suresh N., Methods and apparatus of stacking DRAMs.
  101. Rajan, Suresh N.; Smith, Michael J. S.; Wang, David T, Methods and apparatus of stacking DRAMs.
  102. Dellinger, Eric, Modular array defined by standard cell logic.
  103. Khalid, Mohammed A. S.; Rose, Jonathan, Multi-logic device systems having partial crossbar and direct interconnection architectures.
  104. Rajan, Suresh Natarajan; Smith, Michael John, Multi-rank partial width memory modules.
  105. Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Multi-rank partial width memory modules.
  106. Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Multi-rank partial width memory modules.
  107. Eaton,Bill, Multiple integrated circuit control.
  108. Wang, Min; Ferolito, Philip Arnold; Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Optimal channel design for memory devices for providing a high-speed memory interface.
  109. Wang, Min; Ferolito, Philip Arnold; Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Optimal channel design for memory devices for providing a high-speed memory interface.
  110. Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Performing error detection on DRAMs.
  111. Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Power management of memory circuits by virtual memory simulation.
  112. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Power saving system and method for use with a plurality of memory circuits.
  113. Go Ying W., Programmable high speed routing switch.
  114. Ferolito, Philip Arnold; Rosenband, Daniel L.; Wang, David T.; Smith, Michael John Sebastian, Programming of DIMM termination resistance values.
  115. Ahrens Michael G. (Sunnyvale CA), Ram-logic tile for field programmable gate arrays.
  116. Freeman Richard D. (San Carlos CA), Random access memory (RAM) based configurable arrays.
  117. Kress, Rainer; Buchenrieder, Klaus, Reconfigurable gate array.
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  120. Ting Benjamin S. ; Pani Peter M., Scalable multiple level tab oriented interconnect architecture.
  121. Ting Benjamin S. ; Pani Peter M., Scalable multiple level tab oriented interconnect architecture.
  122. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
  123. Pani, Peter M.; Ting, Benjamin S., Scalable non-blocking switching network for programmable logic.
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  130. Pani,Peter M.; Ting,Benjamin S., Scalable non-blocking switching network for programmable logic.
  131. Smith,Glenn Michael; Bliley,Paul D.; Eaton,Bill; Clark,Walter D., Selectable integrated circuit interface.
  132. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a different number of memory circuit devices.
  133. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a memory standard.
  134. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a memory standard.
  135. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a refresh operation latency.
  136. Wang Steven ; Tseng Ping-Sheng ; Lin Sharon Sheau-Pyng ; Tsay Ren-Song ; Sun Richard Yachyang ; Shen Quincy Kun-Hsu ; Tsai Mike Mon Yen, Simulation server system and method.
  137. Tseng Ping-Sheng ; Lin Sharon Sheau-Pyng ; Shen Quincy Kun-Hsu ; Sun Richard Yachyang ; Tsai Mike Mon Yen ; Tsay Ren-Song ; Wang Steven, Simulation/emulation system and method.
  138. Fjelstad, Joseph C., Stackable low-profile lead frame package.
  139. Wang, David T.; Rajan, Suresh Natarajan, Stacked DIMM memory interface.
  140. Poplevine, Pavel; Lum, Annie-Li-Keow; Zhang, Weipeng; Franklin, Andrew J., Static RAM architecture with bit line partitioning.
  141. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
  142. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
  143. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
  144. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for power management in memory systems.
  145. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for reducing command scheduling constraints of memory circuits.
  146. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for reducing command scheduling constraints of memory circuits.
  147. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for simulating an aspect of a memory circuit.
  148. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for simulating an aspect of a memory circuit.
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  150. Rajan, Suresh Natarajan, System including memory stacks.
  151. Tseng Ping-Sheng ; Lin Sharon Sheau-Ping ; Shen Quincy Kun-Hsu, Timing-insensitive glitch-free logic system and method.
  152. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Translating an address associated with a command communicated between a system and memory circuits.
  153. Wang, David T.; Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Weber, Frederick Daniel, Translating an address associated with a command communicated between a system and memory circuits.
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