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Flexible carrier for an electronic device

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/02
출원번호 US-0198901 (1988-05-26)
발명자 / 주소
  • McBride Donald G. (Binghamton NY) Ellis Theron L. (Vestal NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 30  인용 특허 : 18

초록

The disclosure describes a form of packaging for an electronic device and a method of achieving it in order to overcome the problem of damage because of cycles in environmental temperature. A thin, flexible foil functioning as a carrier of electrically conductive material selected from the group inc

대표청구항

An electronic package assembly, comprising: a flexible carrier formed of a predetermined material that is electrically conductive and has a low coefficient of thermal expansion; a layer of electrically insulating material formed on and supported by said flexible carrier material; an electrical circu

이 특허에 인용된 특허 (18)

  1. Baldwin Graham J. (Cheltenham GB2) McCann Michael O. (Wotton-Under-Edge GB2), Chip-carrier substrates.
  2. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY), Electronic package assembly method.
  3. Reagan John J. (Beaverton OR) Parks Peggy J. (Beaverton OR) Miller Nancy L. (Portland OR) Beckman Robert L. (Beaverton OR), Fabrication of a multilayer conductive pattern on a dielectric substrate.
  4. Barresi Anthony J. (Hammonton NJ) Nelson Leonard (Cherry Hill NJ) Pogson Jack (Toms River NJ), Fixture for solder tinning chip carriers.
  5. Clementi Robert J. (Binghamton NY) Gazdik Charles E. (Endicott NY) Lafer William (Chenango Bridge NY) Lovesky Roy L. (Vestal NY) McBride Donald G. (Binghamton NY) Munson Joel V. (Port Crane NY) Skarv, Flexible film semiconductor chip carrier.
  6. Detoma Renzo B. (Florence ITX), Method to ensure the cooling of electronic components fixed on a multilayer for printed circuits and multilayer realized.
  7. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY), Multi-layer flexible film module.
  8. Leibowitz Joseph D. (Culver City CA), Multilayer printed circuit board structure.
  9. Shirahata Isao (Chigasaki JPX) Shiga Shoji (Utsunomiya JPX) Hori Hisako (Tokyo JPX) Jinbo Takamasa (Odawara JPX), Multilayer printed wiring board and method for producing the same.
  10. Suzuki Hirosuke (Tokorozawa JPX), Printed circuit board.
  11. Oldenettel Jayne L. (Kent WA), Printed wire circuit board and its method of manufacture.
  12. Brown Vernon L. (Boulder CO), Printed wiring board construction.
  13. Kuniya Keiichi (Hitachi JA) Iizuka Tomio (Ibaraki JA) Suwa Masateru (Hitachi JA) Yasuda Tomio (Hitachi JA) Sasaki Takeshi (Hitachi JA) Kikuchi Sakae (Takasaki JA) Suzuki Hideo (Katsuta JA), Semiconductor device having supporting electrode composite structure of metal containing fibers.
  14. Lazzari Jean-Pierre (Montfort l\Amaury FRX), Structure for multilayer circuits.
  15. Jones Keith E. (Aloha OR), Surface mountable microwave IC package.
  16. Yerman Alexander J. (Scotia NY) Loughran James A. (Scotia NY), Tape automated manufacture of power semiconductor devices.
  17. Hodge Robin H. (Menlo Park CA) Brodsky Mark A. (Sunnyvale CA), Thermally balanced leadless microelectronic circuit chip carrier.
  18. DeGree David C. (Burnsville MN) Fick Herbert J. (Northfield MN) Juenger Bruce H. (Northfield MN), Thermally conductive, electrically insulative laminate.

이 특허를 인용한 특허 (30)

  1. Cynthia Susan Milkovich ; Mark Vincent Pierson ; Charles Gerard Woychik, CTE compensated chip interposer.
  2. Lisa J. Jimarez ; Miguel A. Jimarez ; Voya R. Markovich ; Cynthia S. Milkovich ; Charles H. Perry ; Brenda L. Peterson, Compliant layer for encapsulated columns.
  3. Miller Bernhard,DEX ; Roether Friedbert,DEX ; Schneider Norbert,DEX, Conducting foil for conductively connecting electric and/or electronic components.
  4. Beilin Solomon I. ; Chou William T. ; Kudzuma David ; Lee Michael G. ; Peters Michael G. ; Roman James J. ; Swamy Som S. ; Wang Wen-chou Vincent ; Moresco Larry L. ; Murase Teruo, Controlled impedance interposer substrate and method of making.
  5. Beilin Solomon I. ; Chou William T. ; Kudzuma David ; Lee Michael G. ; Peters Michael G. ; Roman James J. ; Swamy Som S. ; Wang Wen-chou Vincent ; Moresco Larry L. ; Murase Teruo, Controlled impedence interposer substrate.
  6. Auerbach, Franz; Gutsmann, Bernd; Licht, Thomas; Seliger, Norbert; Weidner, Karl; Zapf, Jörg, Electrical component on a substrate and method for production thereof.
  7. Brubaker, R. Brad; Humbert, David, Electrical connector system including electrical cable connector assembly.
  8. Alcoe,David, Electronic component test apparatus.
  9. Alcoe David James ; Caletka David Vincent, Electronic component test apparatus with rotational probe.
  10. Alcoe David James ; Caletka David Vincent, Electronic component test apparatus with rotational probe and conductive spaced apart means.
  11. Igor Y. Khandros ; Thomas H. Distefano, Face-up semiconductor chip assemblies.
  12. Yang Rui ; Truong Thach G. ; Mooney Justine A. ; David Moses M., Flexible circuits and carriers and process for manufacture.
  13. Sugiyama, Takahiro; Nounen, Hideki, Flexible harness and electrical connector cable using same.
  14. Pierson, Mark Vincent; Sweterlitsch, Jennifer Rebecca; Woychik, Charles Gerard; Youngs, Jr., Thurston Bryce, Floating interposer.
  15. Zhai,Jun; Kwon,Jinsu; Blish, II,Richard C., Integrated circuit package and method.
  16. Anderson Steven W. ; Armezzani Gregg J. ; Labzentis Daniel P., Method of forming an electrical connection between a conductive member having a dual thickness substrate and a conductor and electronic package including said connection.
  17. Milkovich, Cynthia Susan; Pierson, Mark Vincent; Woychik, Charles Gerard, Method of making a CTE compensated chip interposer.
  18. Jimarez, Lisa J.; Jimarez, Miguel A.; Markovich, Voya R.; Milkovich, Cynthia S.; Perry, Charles H.; Peterson, Brenda L., Method of making an electronic package.
  19. Jimarez,Lisa J.; Jimarez,Miguel A.; Markovich,Voya R.; Milkovich,Cynthia S.; Perry,Charles H.; Peterson,Brenda L., Method of making an electronic package.
  20. Pierson, Mark Vincent; Sweterlitsch, Jennifer Rebecca; Woychik, Charles Gerard; Youngs, Jr., Thurston Bryce, Methods of making and using a floating interposer.
  21. Igor Y. Khandros ; Thomas H. Distefano, Methods of making semiconductor chip assemblies.
  22. Khandros Igor Y. ; Distefano Thomas H., Methods of making semiconductor chip assemblies.
  23. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  24. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  25. Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Semiconductor chip assemblies, methods of making same and components for same.
  26. Khandros,Igor Y.; DiStefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
  27. Khandros,Igor Y.; Distefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
  28. Igor Y. Khandros ; Thomas H. DiStefano, Semiconductor chip assembly with anisotropic conductive adhesive connections.
  29. Khandros Igor Y. ; Distefano Thomas H., Semiconductor chip package with center contacts.
  30. Igor Y. Khandros ; Thomas H. DiStefano, Stacked chip assembly.
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