초록 ▼

The present invention is directed to a three-dimensional stacked IC and a method for forming a three-dimensional stacked IC on a base plate. The three-dimensional stacked IC includes a unit semiconductor IC, which has constituent ICs formed on either one surface or on both surfaces of a substrate. I

The present invention is directed to a three-dimensional stacked IC and a method for forming a three-dimensional stacked IC on a base plate. The three-dimensional stacked IC includes a unit semiconductor IC, which has constituent ICs formed on either one surface or on both surfaces of a substrate. In addition, the unit semiconductor ICs have a plurality of conducting posts buried in and penetrating through the substrate and insulated therefrom. The unit semiconductor ICs have interconnection terminals provided on both sides of the substrate for connecting other unit semiconductor ICs or a base plate. By stacking plural unit ICs on the base plate, a very large scale IC can be fabricated. Each constituent IC is formed on a bulk silicon substrate, therefore excellent quality can be obtained. This can be also applied to the fabrication of a ROM structure such as a PROM or MASK ROM, using single unit semiconductor ICs, wherein a wiring for the ROM can be formed on the second surface of the substrate.

대표청구항 ▼

A semiconductor integrated circuit comprising: a plurality of unit semiconductor integrated circuits stacked together, each of said unit semiconductor integrated circuits comprising: a substrate having first and second surfaces, said second surface having a smooth mirror finish; an integrated circui

A semiconductor integrated circuit comprising: a plurality of unit semiconductor integrated circuits stacked together, each of said unit semiconductor integrated circuits comprising: a substrate having first and second surfaces, said second surface having a smooth mirror finish; an integrated circuit including at least one of an active and passive functional element, formed on at least said first surface of said substrate; a conducting post having first and second end portions, said conducting post penetrating through said substrate to said first and second surfaces, and insulated therefrom; and a wiring, formed on said first and second surfaces of said substrate including said conducting post and said integrated circuit, being selectively connected to said integrated circuit and to said first and second end portions of said conducting post; an insulating layer, formed on the surface of said unit semiconductor integrated circuits, for connecting two adjacent ones of said plurality of unit semiconductor integrated circuits; and an interconnection terminal, formed in said insulating layer and extending to said wiring, for connecting said two adjacent ones of said plurality of unit semiconductor integrated circuits.