초록

A communications receiver, wherein an elastic store FIFO buffers clock-phase jitter. A jitter estimate is obtained by a very simple circuit, wherein the read clock is used as a reference to sample the FIFO address pointers.

대표청구항 ▼

A communications receiver, for receiving incoming synchronous data streams, comprising: a first clock recovery circuit, which generates a first estimated clock signal from the incoming data stream; a second clock recovery circuit, which generates a second estimated clock signal from the incoming dat

A communications receiver, for receiving incoming synchronous data streams, comprising: a first clock recovery circuit, which generates a first estimated clock signal from the incoming data stream; a second clock recovery circuit, which generates a second estimated clock signal from the incoming data stream, said second estimated clock signal being more highly filtered than said first estimated clock signal and having substantially the same average frequency as said first estimated clock signal; a serial-access memory, configured to operate such that successive bits of the incoming data are written, with a timing governed by said first estimated clock signal, into address locations specified by the current value of a write-address-pointer which is incremented at each said write operation, and successive bits are read out, with a timing governed by said second clock signal, from an address location specified by the current value of a read-address-pointer which is incremented at each said read operation; and a counter, clocked by said second estimated clock signal, and having a reset input which is connected to reset whenever said write-address-pointer value crosses a predetermined value, and having an output which is connected, through a latch circuit, to be latched whenever said read-address-pointer value crosses a predetermined value, the successive latched outputs of said counter providing an estimate of jitter.