초록 ▼

An electrically programmable floating gate transistor useful as a one transistor flash EPROM cell includes a multi-thickness dielectric provided on a substrate. The multi-thickness dielectric limits tunnelling from a floating gate provided on the multi-thickness dielectric to a drain during programm

An electrically programmable floating gate transistor useful as a one transistor flash EPROM cell includes a multi-thickness dielectric provided on a substrate. The multi-thickness dielectric limits tunnelling from a floating gate provided on the multi-thickness dielectric to a drain during programming and allowing tunnelling from the floating gate to the source during erasing. The floating gate has a low doping concentration, less than 5×1018 cm-3, and a thickness of less than 1000 Åto provide a self-limiting erase characteristic.

대표청구항 ▼

An electrically programmable and erasable semiconductor device, provided on a substrate, comprising: a drain region provided in the substrate; a source region provided in the substrate, said source region comprising a first lightly doped source region and a second heavily doped source region provide

An electrically programmable and erasable semiconductor device, provided on a substrate, comprising: a drain region provided in the substrate; a source region provided in the substrate, said source region comprising a first lightly doped source region and a second heavily doped source region provided in said first source region and being spaced from said drain region to define a channel region therebetween; dielectric means for limiting tunnelling during programming and allowing tunnelling during erasing, said dielectric means comprising a tunnelling dielectric having a first thickness provided on a portion of the substrate corresponding to the position of a portion of said source region and a gate oxide having a second thickness greater than said first thickness provided on a portion of the substrate corresponding to the position of a portion of said channel and a portion of said drain region; a floating gate provided on said dielectric means; an inter-gate dielectric provided on said floating gate; and a control gate provided on said inter-gate dielectric.