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Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-005/00
출원번호 US-0337807 (1989-04-14)
발명자 / 주소
  • Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 152  인용 특허 : 0

초록 ▼

A process of forming a multi-level semiconductor metallization structure from a single deposit layer of metal. The process provides the versatility of allowing stud-up, stud-down, thick and/or thin metallization structure lines to be formed from the single layer of metal. The thick metallization str

대표청구항 ▼

A process for forming a multi-level metallization structure on a processed semiconductor substrate, comprising the steps of: forming a planar insulating layer on said processed semiconductor substrate; masking and etching said planar insulating layer to form a plurality of wiring troughs in an upper

이 특허를 인용한 특허 (152)

  1. Liu Erzhuang,SGX, Air gap formation for high speed IC processing.
    상세보기
  2. Wang Hsingya Arthur ; Zhou Qimeng, Block select transistor and method of fabrication.
    상세보기
  3. Farrar,Paul A.; Geusic,Joseph, Buried conductor patterns formed by surface transformation of empty spaces in solid state materials.
    상세보기
  4. Glenn A. Rinne ; Paul A. Magill, Controlled-shaped solder reservoirs for increasing the volume of solder bumps.
    상세보기
  5. Glenn A. Rinne ; Paul A. Magill, Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby.
    상세보기
  6. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
    상세보기
  7. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
    상세보기
  8. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
    상세보기
  9. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
    상세보기
  10. Farrar Paul A., Copper metallurgy in integrated circuits.
    상세보기
  11. Farrar, Paul A., Copper metallurgy in integrated circuits.
    상세보기
  12. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
    상세보기
  13. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
    상세보기
  14. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.
    상세보기
  15. Ahn,Kie Y.; Forbes,Leonard, Electronic apparatus with deposited dielectric layers.
    상세보기
  16. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.
    상세보기
  17. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.
    상세보기
  18. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.
    상세보기
  19. Ahn, Kie Y.; Forbes, Leonard, Films deposited at glancing incidence for multilevel metallization.
    상세보기
  20. Ahn,Kie Y.; Forbes,Leonard, Films deposited at glancing incidence for multilevel metallization.
    상세보기
  21. Ahn,Kie Y.; Forbes,Leonard, Films deposited at glancing incidence for multilevel metallization.
    상세보기
  22. James G. Ryan ; Badih El-Kareh, Flexible interconnections with dual-metal dual-stud structure.
    상세보기
  23. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
    상세보기
  24. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
    상세보기
  25. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper and other metals.
    상세보기
  26. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
    상세보기
  27. Farrar, Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
    상세보기
  28. Dixit, Pankaj; Horel, Timothy; Li, Mu-Jing; Vercruysse, Ward, Grounded fill in a large scale integrated circuit.
    상세보기
  29. Farrar,Paul A., Hplasma treatment.
    상세보기
  30. Farrar,Paul A., Hydrophobic foamed insulators for high density circuits.
    상세보기
  31. Farrar, Paul A., Insulators for high density circuits.
    상세보기
  32. Farrar, Paul A., Insulators for high density circuits.
    상세보기
  33. Farrar, Paul A., Integrated circuit and seed layers.
    상세보기
  34. Farrar,Paul A., Integrated circuit and seed layers.
    상세보기
  35. Farrar,Paul A., Integrated circuit and seed layers.
    상세보기
  36. Cronin John Edward, Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same.
    상세보기
  37. Cronin, John Edward; Hiltebeitel, John Andrew; Kaanta, Carter Welling; Ryan, James Gardner, Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same.
    상세보기
  38. Dennison,Charles H.; Doan,Trung T., Integrated circuit contact.
    상세보기
  39. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
    상세보기
  40. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
    상세보기
  41. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
    상세보기
  42. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
    상세보기
  43. Farrar, Paul A., Integrated circuit device structure including foamed polymeric material.
    상세보기
  44. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit which uses a damascene process for producing staggered interconnect lines.
    상세보기
  45. Farrar Paul A., Integrated circuit with oxidation-resistant polymeric layer.
    상세보기
  46. Stolmeijer Andre, Interconnect scheme for integrated circuits.
    상세보기
  47. Rinne Glenn A. ; Mis Joseph Daniel, Key-shaped solder bumps and under bump metallurgy.
    상세보기
  48. Farrar, Paul A., Low dielectric constant STI with SOI devices.
    상세보기
  49. Farrar, Paul A., Low dielectric constant STI with SOI devices.
    상세보기
  50. Farrar, Paul A., Low dielectric constant shallow trench isolation.
    상세보기
  51. Farrar, Paul A., Low dielectric constant shallow trench isolation.
    상세보기
  52. Farrar, Paul A., Low dielectric constant shallow trench isolation.
    상세보기
  53. Farrar, Paul A., Low dielectric constant shallow trench isolation.
    상세보기
  54. Farrar, Paul A., Low dielectric constant shallow trench isolation.
    상세보기
  55. Paul A. Farrar, Low dielectric constant shallow trench isolation.
    상세보기
  56. Geusic, Joseph E.; Farrar, Paul A.; Bhattacharyya, Arup, Low k interconnect dielectric using surface transformation.
    상세보기
  57. Geusic,Joseph E.; Farrar,Paul A.; Bhattacharyya,Arup, Low k interconnect dielectric using surface transformation.
    상세보기
  58. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.
    상세보기
  59. Farrar, Paul A., Mask on a polymer having an opening width less than that of the opening in the polymer.
    상세보기
  60. Farrar, Paul A., Memory system with conductive structures embedded in foamed insulator.
    상세보기
  61. Dennison, Charles H.; Doan, Trung T., Method for an integrated circuit contact.
    상세보기
  62. Dennison, Charles H.; Doan, Trung T., Method for an integrated circuit contact.
    상세보기
  63. Dennison, Charles H; Doan, Trung T., Method for an integrated circuit contact.
    상세보기
  64. Dennison,Charles H; Doan,Trung T., Method for an integrated circuit contact.
    상세보기
  65. Dennison,Charles H; Doan,Trung T., Method for an integrated circuit contact.
    상세보기
  66. Yuan, Xuejun; Jin, Xiaowei; Pyapali, Rambabu; Heald, Raymond A.; Kaku, James M.; Dunn, Helen; Taylor, Thelma C.; Lai, Peter F.; Ostrer, Aharon, Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug.
    상세보기
  67. Becker,David S.; Blalock,Guy T.; Roe,Fred L., Method for enhancing silicon dioxide to silicon nitride selectivity.
    상세보기
  68. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
    상세보기
  69. Dubin, Valery, Method for making interconnects and diffusion barriers in integrated circuits.
    상세보기
  70. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials.
    상세보기
  71. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials.
    상세보기
  72. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon.
    상세보기
  73. Ryan James G. ; El-Kareh Badih, Method of making flexible interconnections with dual-metal-dual-stud structure.
    상세보기
  74. Tuttle Mark E. ; Doan Trung Tri, Method of passivating semiconductor wafers.
    상세보기
  75. Naik Mehul ; Broydo Samuel, Method of producing an interconnect structure for an integrated circuit.
    상세보기
  76. Naik, Mehul; Broydo, Samuel, Method of producing an interconnect structure for an integrated circuit.
    상세보기
  77. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  78. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  79. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  80. Kie Y. Ahn ; Leonard Forbes, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  81. Glenn A. Rinne ; Joseph Daniel Mis, Methods for forming integrated redistribution routing conductors and solder bumps.
    상세보기
  82. Ahn Kie Y. ; Forbes Leonard, Methods for making copper and other metal interconnections in integrated circuits.
    상세보기
  83. Ahn,Kie Y.; Forbes,Leonard, Methods for making copper and other metal interconnections in integrated circuits.
    상세보기
  84. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  85. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  86. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  87. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.
    상세보기
  88. Cronin John Edward, Methods for the preparation of a semiconductor structure having multiple levels of self-aligned interconnection metalliz.
    상세보기
  89. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  90. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  91. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.
    상세보기
  92. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.
    상세보기
  93. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.
    상세보기
  94. Rinne,Glenn A., Methods of providing solder structures for out plane connections.
    상세보기
  95. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.
    상세보기
  96. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture.
    상세보기
  97. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture.
    상세보기
  98. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package with conductive elements and associated method of manufacture.
    상세보기
  99. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device with package with conductive elements and associated method of manufacture.
    상세보기
  100. Rinne Glenn A. ; Deane Philip A., Microelectronic packaging using arched solder columns.
    상세보기
  101. Rinne Glenn A. ; Deane Philip A., Microelectronic packaging using arched solder columns.
    상세보기
  102. Rinne Glenn A., Microelectronic radiation detectors for detecting and emitting radiation signals.
    상세보기
  103. Farrar, Paul A.; Eldridge, Jerome M., Multi-chip electronic package and cooling system.
    상세보기
  104. Farrar, Paul A.; Eldridge, Jerome M., Multi-chip electronic package and cooling system.
    상세보기
  105. Farrar, Paul A.; Eldridge, Jerome M., Multi-chip electronic package and cooling system.
    상세보기
  106. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
    상세보기
  107. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
    상세보기
  108. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
    상세보기
  109. Farrar, Paul A.; Eldridge, Jerome M., Multiple chip stack structure and cooling system.
    상세보기
  110. Farrar, Paul A.; Eldridge, Jerome M., Multiple chip stack structure and cooling system.
    상세보기
  111. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.
    상세보기
  112. Rinne,Glenn A., Optical structures including liquid bumps and related methods.
    상세보기
  113. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
    상세보기
  114. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
    상세보기
  115. Smith Gregory C. ; Bonifield Thomas D., Planarized selective tungsten metallization system.
    상세보기
  116. Farrar, Paul A., Polynorbornene foam insulation for integrated circuits.
    상세보기
  117. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  118. Paul A. Farrar, Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy.
    상세보기
  119. Bhattacharyya, Arup; Geusic, Joseph E., Scalable high performance antifuse structure and process.
    상세보기
  120. Bhattacharyya, Arup; Geusic, Joseph E., Scalable high performance antifuse structure and process.
    상세보기
  121. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
    상세보기
  122. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
    상세보기
  123. Cho, Young-Jin, Semiconductor device.
    상세보기
  124. Cho, Young-Jin, Semiconductor device.
    상세보기
  125. Dennison,Charles H.; Doan,Trung T., Semiconductor device having integrated circuit contact.
    상세보기
  126. Nam, Tae-Duk; Kim, Jin-Ho; Kim, Hyuk-Su; Kim, Hyoung-Suk; Lee, Tae-Young, Semiconductor package having supporting plate and method of forming the same.
    상세보기
  127. Nam, Tae-Duk; Kim, Jin-Ho; Kim, Hyuk-Su; Kim, Hyoung-Suk; Lee, Tae-Young, Semiconductor package having supporting plate and method of forming the same.
    상세보기
  128. Cronin John Edward (Milton VT), Semiconductor structure having multiple levels of self-aligned interconnection metallization, and methods for its prepar.
    상세보기
  129. Rinne Glenn A. ; Mis Joseph Daniel, Solder bumps and structures for integrated redistribution routing conductors.
    상세보기
  130. Rinne, Glenn A., Solder structures for out of plane connections.
    상세보기
  131. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.
    상세보기
  132. Rinne,Glenn A., Stacked electronic structures including offset substrates.
    상세보기
  133. Farrar, Paul A., Structures and methods to enhance copper metallization.
    상세보기
  134. Farrar, Paul A., Structures and methods to enhance copper metallization.
    상세보기
  135. Farrar, Paul A., Structures and methods to enhance copper metallization.
    상세보기
  136. Farrar,Paul A., Structures and methods to enhance copper metallization.
    상세보기
  137. Farrar,Paul A., Structures and methods to enhance copper metallization.
    상세보기
  138. Paul A. Farrar, Structures and methods to enhance copper metallization.
    상세보기
  139. Bhattacharyya, Arup; Farrar, Paul A., Techniques to create low K ILD for BEOL.
    상세보기
  140. Bhattacharyya,Arup; Farrar,Paul A., Techniques to create low K ILD for BEOL.
    상세보기
  141. Bhattacharyya,Arup; Farrar,Paul A., Techniques to create low K ILD for beol.
    상세보기
  142. Bhattacharyya,Arup; Farrar,Paul A., Techniques to create low K ILD forming voids between metal lines.
    상세보기
  143. Farrar, Paul A., Testing of multi-chip electronic modules.
    상세보기
  144. Farrar,Paul A., Three-dimensional multichip module.
    상세보기
  145. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  146. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  147. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  148. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  149. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  150. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  151. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  152. Tang, Yu-Po; Chang, Shih-Ming; Hsieh, Ken-Hsien; Liu, Ru-Gun, Via-free interconnect structure with self-aligned metal line interconnections.
    상세보기

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