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Method for fabricating double implanted LDD transistor self-aligned with gate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/265
출원번호 US-0428155 (1989-11-24)
발명자 / 주소
  • Huang Tiao-Yuan (Cupertino CA)
출원인 / 주소
  • Xerox Corporation (Stamford CT 02)
인용정보 피인용 횟수 : 67  인용 특허 : 2

초록

An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment member and a heavily doped junctio

대표청구항

A method for fabricating LDD transistor devices comprising the steps of: providing a semiconductor substrate of a first conductivity type, forming a gate insulating film on said semiconductor substrate, forming a thin conductive layer upon said gate insulating film, forming a thick alignment member

이 특허에 인용된 특허 (2)

  1. Chao Fung-Ching (Taiwan CNX), Ladder gate LDDFET.
  2. Chao Fung-Ching (Tainan Shih TWX), Method of fabricating a LDDFET with self-aligned silicide.

이 특허를 인용한 특허 (67)

  1. Dorleans Fernand (Wappingers Falls NY) Hsia Liang-Choo (Stormville NY) Hsu Louis L. C. (Fishkill NY) Larsen Gerald R. (Cornwall NY) Schwartz Geraldine C. (Poughkeepsie NY), CMOS transistor with two-layer inverse-T tungsten gate.
  2. Yamazaki, Shunpei, Device comprising EL element electrically connected to P-channel transistor.
  3. Church Michael D. ; Ito Akira, Double diffused MOS device and method.
  4. Gardner Mark I. ; Bush John J. ; Cheek Jon D., Formation and control of a vertically oriented transistor channel length.
  5. Yamazaki, Shunpei; Fukunaga, Takeshi; Koyama, Jun; Inukai, Kazutaka, Light emitting device and fabricating method thereof.
  6. Yamazaki,Shunpei; Fukunaga,Takeshi; Koyama,Jun; Inukai,Kazutaka, Light emitting device and fabrication method thereof.
  7. Yamazaki, Shunpei; Fukunaga, Takeshi; Koyama, Jun; Inukai, Kazutaka, Light emitting device and manufacturing method thereof.
  8. Yamazaki, Shunpei; Fukunaga, Takeshi; Koyama, Jun; Inukai, Kazutaka, Light emitting device and manufacturing method thereof.
  9. Yamazaki, Shunpei, Light-emitting device having a triple-layer wiring structure.
  10. Monoe, Shigeharu; Yokoshima, Takashi; Sasagawa, Shinya, Manufacturing method for semiconductor device.
  11. Monoe,Shigeharu; Yokoshima,Takashi; Sasagawa,Shinya, Manufacturing method for semiconductor device.
  12. Monoe,Shigeharu; Yokoshima,Takashi; Sasagawa,Shinya, Manufacturing method for semiconductor device.
  13. Monoe,Shigeharu; Yokoshima,Takashi; Sasagawa,Shinya, Manufacturing method for semiconductor device.
  14. Dorleans Fernand (Wappingers Falls NY) Hsia Liang-Choo (Stormville NY) Hsu Louis L. C. (Fishkill NY) Larsen Gerald R. (Cornwall NY) Schwartz Geraldine C. (Poughkeepsie NY), Method for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure.
  15. Liao Siu-han (Hsia-chu TWX), Method for fabricating flat ROM devices using memory array cells with concave channels.
  16. Chen Coming,TWX ; Yeh Wen-Kuan,TWX ; Chou Jih-Wen,TWX, Method for forming a metal-oxide-semiconductor transistor.
  17. Wu Shye-Lin,TWX, Method for forming a semiconductor device with an inverse-T gate lightly-doped drain structure.
  18. Wu Shye-Lin (Hsinchu TWX), Method for forming inverse-T gate lightly-doped drain (ITLDD) device.
  19. Yu Chen-Hua,TWX ; Tsai Chia-Shiung,TWX, Method of fabricating a narrow polycide gate structure on an ultra-thin gate insulator layer.
  20. Yamazaki, Shunpei, Method of fabricating a semiconductor device.
  21. Yamazaki, Shunpei, Method of fabricating a semiconductor device.
  22. Yamazaki, Shunpei, Method of fabricating a semiconductor device.
  23. Hsue Chen-Chiu,TWX ; Chien Sun-Chieh,TWX, Method of forming a capacitor.
  24. Yamazaki, Shunpei; Ohtani, Hisashi; Suzawa, Hideomi; Takayama, Toru, Method of forming a semiconductor device.
  25. Yamazaki,Shunpei, Method of forming insulating films, capacitances, and semiconductor devices.
  26. Satoh Shinichi (Hyogo-ken JPX) Ozaki Hiroji (Hyogo-ken JPX) Eimori Takahisa (Hyogo-ken JPX), Method of making a field effect transistor with a T shaped polysilicon gate electrode.
  27. Spikes Thomas E. ; Gardner Mark I. ; Fulford ; Jr. H. Jim, Method of making high performance mosfets having high conductivity gate conductors.
  28. Verhaar Robertus D. J. (Eindhoven NLX), Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted “T”.
  29. Verhaar Robertus D. J. (Eindhoven NLX), Method of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source.
  30. Sasagawa,Shinya; Yokoshima,Takashi; Monoe,Shigeharu, Method of manufacturing a semiconductor device.
  31. Yamazaki,Shunpei, Method of manufacturing a semiconductor device having a gate electrode with a three layer structure.
  32. Kamijo Hiroyuki (Yokohama JPX) Usami Toshiro (Yokohama JPX) Mikata Yuuichi (Kawasaki JPX), Method of manufacturing semiconductor device.
  33. Lin Tony,TWX ; Yeh Wen-Kuan,TWX ; Chou Jih-Wen,TWX, Method of suppressing junction capacitance of source/drain regions.
  34. Wu Shye-Lin,TWX, Method to form mosfet with an inverse T-shaped air-gap gate structure.
  35. Kittl, Jorge Adrian; Hong, Qi-Zhong, Method to improve silicide formation on polysilicon.
  36. Hamm, Thomas; Mueller, Beno, Optical device.
  37. Liu, Donghua; Qian, Wensheng, Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor.
  38. Shunpei Yamazaki JP, Semiconductor device.
  39. Yamazaki, Shunpei, Semiconductor device.
  40. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  41. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  42. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  43. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  44. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device and fabrication method thereof.
  45. Suzawa, Hideomi; Ono, Koji; Takayama, Toru; Arao, Tatsuya; Yamazaki, Shunpei, Semiconductor device and manufacturing method thereof.
  46. Suzawa,Hideomi; Ono,Koji; Takayama,Toru; Arao,Tatsuya; Yamazaki,Shunpei, Semiconductor device and manufacturing method thereof.
  47. Suzawa,Hideomi; Ono,Koji; Takayama,Toru; Arao,Tatsuya; Yamazaki,Shunpei, Semiconductor device and manufacturing method thereof.
  48. Suzawa, Hideomi; Ono, Koji; Takayama, Toru, Semiconductor device and method for manufacturing same.
  49. Suzawa, Hideomi; Ono, Koji; Takayama, Toru, Semiconductor device and method for manufacturing same.
  50. Suzawa, Hideomi; Ono, Koji; Takayama, Toru, Semiconductor device and method for manufacturing the same.
  51. Shunpei Yamazaki JP; Jun Koyama JP, Semiconductor device and method of fabricating the same.
  52. Yamazaki, Shunpei; Koyama, Jun, Semiconductor device and method of fabricating the same.
  53. Yamazaki, Shunpei; Koyama, Jun, Semiconductor device and method of fabricating the same.
  54. Yamazaki, Shunpei; Koyama, Jun, Semiconductor device and method of fabricating the same.
  55. Yamazaki, Shunpei; Koyama, Jun, Semiconductor device and method of fabricating the same.
  56. Yamazaki, Shunpei; Koyama, Jun, Semiconductor device and method of fabricating the same.
  57. Yamazaki, Shunpei; Koyama, Jun, Semiconductor device and method of fabricating the same.
  58. Yamazaki,Shunpei; Koyama,Jun, Semiconductor device and method of fabricating the same.
  59. Yamazaki,Shunpei; Ohtani,Hisashi; Suzawa,Hideomi; Takayama,Toru, Semiconductor device and method of fabricating the same.
  60. Yamazaki, Shunpei; Arai, Yasuyuki; Koyama, Jun, Semiconductor device comprising a pixel unit including an auxiliary capacitor.
  61. Yamazaki,Shunpei, Semiconductor device comprising thin film transistor comprising conductive film having tapered edge.
  62. Mukai Takao (Hyogo-ken JPX) Yoshioka Nobuyuki (Hyogo-ken JPX), Semiconductor device having diffusion regions formed with an ion beam absorber pattern.
  63. Suzawa,Hideomi; Ono,Koji; Takayama,Toru, Semiconductor device that includes a gate insulating layer with three different thicknesses.
  64. Yamazaki, Shunpei, Semiconductor device with tapered gates.
  65. Ohnuma, Hideto, Semiconductor display device and manufacturing method thereof.
  66. Yamazaki Shunpei,JPX, Semiconductor memory device including a field effect transistor.
  67. Park, Nam Kyu, Transistor in a semiconductor substrate having high-concentration source and drain region formed at the bottom of a trench adjacent to the gate electrode.
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