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A process for forming an integrated circuit pin grid array package comprising a flexible metal tape adapted for use in tape automated bonding with a plurality of holes. Terminal pins are inserted in the holes and the tapes and pins are disposed within a mold so that a cavity is formed about the pins

A process for forming an integrated circuit pin grid array package comprising a flexible metal tape adapted for use in tape automated bonding with a plurality of holes. Terminal pins are inserted in the holes and the tapes and pins are disposed within a mold so that a cavity is formed about the pins and tape. The cavity is filled with a polymer resin so as to at least partially surround and support the pins and tape and thereby form the plastic encapsulated pin grid array.

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A process for forming an integrated circuit pin grid array package, comprising the steps of: providing an interconnect tape having first and second opposing surfaces, said first surface having a metal circuit pattern defining a plurality of leads; forming a plurality of holes of a first diameter in

A process for forming an integrated circuit pin grid array package, comprising the steps of: providing an interconnect tape having first and second opposing surfaces, said first surface having a metal circuit pattern defining a plurality of leads; forming a plurality of holes of a first diameter in said metal circuit pattern; providing a plurality of pins, said pins defined by a pin head end of a second diameter, an insertion end and a collar of a third diameter disposed therebetween, said collar defined by first and second shoulder wherein said third diameter is larger than said first diameter and said first diameter is larger than said second diameter; inserting said insertion end of said pin into a first fixture; placing said interconnect tape over said pin head end such that said holes in said circuit pattern encircle said pin heads and said interconnect tape rests on said first shoulder of said pins; and soldering said pins to said interconnect tape using a mask to control said solder.