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Hermetic microminiature packages 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/06
  • H01L-023/14
출원번호 US-0188322 (1988-05-04)
발명자 / 주소
  • Butt Sheldon H. (Godfrey IL)
출원인 / 주소
  • International Electronic Research Corp. (Burbank CA 02)
인용정보 피인용 횟수 : 42  인용 특허 : 16

초록

A hermetic tape package and a process for forming the hermetic tape package are disclosed. The package is capable of high lead densities and occupies a minimum of space. A test frame is incorporated into the package to permit testing of an electronic device prior to sealing the package.

대표청구항

A test frame adapted to support and electrically connect to an electronic device, comprising: a first ring frame containing a plurality of interior slots incompletely circumscribing a central portion of said first ring frame and a plurality of external slots incompletely circumscribing both said cen

이 특허에 인용된 특허 (16)

  1. Lindberg Frank A. (Catonsville MD), Apparatus and method for tape bonding and testing of integrated circuit chips.
  2. Gursky Michael T. (Allentown PA), Carrier tapes for semiconductor devices.
  3. Mahulikar Deepak (Meriden CT) Cherukuri Satyam C. (West Haven CT), Graded sealing systems for semiconductor package.
  4. Butt Sheldon H. (Godfrey IL), Hermetically sealed semiconductor casing.
  5. Pryor Michael J. (Woodbridge CT) Eppler Richard A. (Cheshire CT) Smith ; III Edward F. (Madison CT) Butt Sheldon H. (Godfrey IL), Hermetically sealed semiconductor package.
  6. Emamjomeh Ali (Sunnyvale CA) Pice Richard (Los Altos Hills CA), Hinge tape.
  7. Devlin Daniel J. (Torrance CA), Integrated circuit package and lead frame.
  8. Grabbe Dimitry (Lisbon Falls ME) Patterson Ronald (Dauphin PA), Lead frame and chip carrier housing.
  9. Burns Carmen D. (San Jose CA), Manufacture of bumped composite tape for automatic gang bonding of semiconductor devices.
  10. Caron Ronald N. (Branford CT) Breedis John F. (Trumbull CT), Multipurpose copper alloys with moderate conductivity and high strength.
  11. Sankhagowit Thanomsak (Sunnyvale CA), Pre-testable semiconductor die package.
  12. Saleh Yousef (West Haven CT) Breedis John F. (Trumbull CT) Crane Jacob (Woodbridge CT), Precipitation hardenable copper alloy and process.
  13. Butt Sheldon H. (Godfrey IL), Semiconductor packages.
  14. Jung James E. (Westfield IN) Koors Mark A. (Kokomo IN) Lutz Phillip A. (Kokomo IN), Surface mount package for encapsulated tape automated bonding integrated circuit modules.
  15. Butt Sheldon H. (Godfrey IL), Tape packages.
  16. Barber Larry J. (Sunnyvale CA), Testable tape for bonding leads to semiconductor die and process for manufacturing same.

이 특허를 인용한 특허 (42)

  1. Mahulikar Deepak (Madison CT) Sagiv Efraim (Meriden CT) Parthasarathi Arvind (North Branford CT) Jalota Satish (Wallingford CT) Brock Andrew J. (Cheshire CT) Holmes Michael A. (Ripon CA) Schlater Jef, Anodized aluminum substrate having increased breakdown voltage.
  2. Goren, Yehuda G.; Chen, Tong, Asymmetrical slow wave structures to eliminate backward wave oscillations in wideband traveling wave tubes.
  3. Hoffman Paul R. (Modesto CA) Mahulikar Deepak (Madison CT) Brathwaite George A. (Hayward CA) Solomon Dawit (Manteca CA) Parthasarathi Arvind (North Branford CT), Components for housing an integrated circuit device.
  4. Akram, Salman, Copper interconnect.
  5. Akram,Salman, Copper interconnect.
  6. Akram,Salman, Copper interconnect.
  7. Akram,Salman, Copper interconnect for semiconductor device.
  8. Hoffman Paul R. ; Popplewell James M. ; Braden Jeffrey S., Edge connectable metal package.
  9. Parthasarathi Arvind (North Branford CT), Electronic package with improved thermal properties.
  10. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
  11. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
  12. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
  13. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip and method of manufacture.
  14. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip and method of manufacture.
  15. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip in wafer form.
  16. Farnworth Warren M., Hermetically sealed chip scale packages formed by wafer level fabrication and assembly.
  17. Silverbrook,Kia, Integrated circuit carrier.
  18. Silverbrook, Kia, Integrated circuit carrier arrangement with electrical connection islands.
  19. Lee, Michael; Yamamoto, Takuji, Interposer for integrated circuit chip package.
  20. Crook Russell A., Mercaptofunctional silanes to deposit sol-gel coatings on metals.
  21. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.
  22. Bustrich Gunther,SEX ; Lundstrom Lars Erik Pontus,SEX, Method for mounting a circuit.
  23. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  24. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  25. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  26. Chen, Tong; Chai, Suchet P., Method of packaging a device with a lead frame, and an apparatus formed therefrom.
  27. Tandy,William D.; Street,Bret K., Methods for marking a bare semiconductor die including applying a tape having energy-markable properties.
  28. Tandy,William D.; Street,Bret K., Methods for marking a packaged semiconductor die including applying tape and subsequently marking the tape.
  29. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.
  30. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.
  31. Williams, Anthony David, Noise canceling technique for frequency synthesizer.
  32. August, Melvin C.; Christie, Diane M.; Hebert, Arthur J.; Neumann, Eugene F.; Steitz, Richard R., Non-metallized chip carrier.
  33. Liang Louis H., Reinforced leadframe to substrate attachment.
  34. Yu, Shang-Cheng; Cheng, Chih-Nan, Semiconductor device.
  35. Akram, Salman, Semiconductor device having copper interconnect for bonding.
  36. Goren, Yehuda G.; Lally, Philip M., Slow wave structure having offset projections comprised of a metal-dielectric composite stack.
  37. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  38. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  39. Connell, Michael E.; Jiang, Tongbi, Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive.
  40. Connell,Michael E.; Jiang,Tongbi, Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive.
  41. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
  42. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
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