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An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to tempora

An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

대표청구항 ▼

A bus arbitration control circuit for a computer system having a microprocessor, a system memory and a shared bus between the microprocessor and the system memory, said computer system further including a memory refresh control circuit that uses said shared bus to periodically refresh said system me

A bus arbitration control circuit for a computer system having a microprocessor, a system memory and a shared bus between the microprocessor and the system memory, said computer system further including a memory refresh control circuit that uses said shared bus to periodically refresh said system memory and at least first and second peripheral controllers that use said shared bus to transfer data between said system memory and first and second peripheral devices, respectively, said bus arbitration control circuit arbitrating control of said shared bus, said arbitration control circuit comprising: a first input connected to receive a refresh request signal from said memory refresh control circuit, said memory refresh control circuit activating said refresh request signal when said memory refresh control circuit wants control of said shared bus to refresh said system memory; a second input connected to receive a first bus request signal from said first peripheral controller, said first peripheral controller activating said first bus request signal when said first peripheral controller wants control of said shared bus to transfer data between said system memory and said first principal device; a third input connected to receive a second bus request signal from said second peripheral controller, said second peripheral controller activating said second bus request signal when said second peripheral controller wants control of said shared bus to transfer data between said system memory and said second peripheral device; a first output connected to provide a hold request signal to said microprocessor, said bus arbitration control circuit activating said hold request signal to request said microprocessor to relinquish control of said shared bus; arbitration relinquishing means to return control of the shared bus back to the microprocessor; a fourth input connected to receive a hold acknowledge signal from said microprocessor, said microprocessor activating said hold acknowledge signal to inform said bus arbitration control circuit that said microprocessor has relinquished control of said shared bus; a second output connected to provide a refresh grant signal to said memory refresh control circuit, said bus arbitration control circuit activating said refresh grant signal to inform said memory refresh control circuit that it has control of the shared bus; a third output connected to provide a first bus grant signal to said first peripheral controller, said bus arbitration control circuit activating said first bus grant signal to inform said first peripheral controller that it has control of the shared bus; a fourth output connected to provide a second bus grant signal to said second peripheral controller, said bus arbitration control circuit activating said second bus grant signal to inform said second peripheral controller that it has control of the shared bus; and a logic sequencer that monitors said refresh request signal, said first bus request signal, said second bus request signal and said hold knowledge signal on said first, second, third and fourth inputs, respectively, and that generates said active hold request signal, said refresh grant signal, said first bus grant signal and said second bus grant signal on said first, second third and fourth outputs, respectively, said logic sequencer responsive to active refresh request, first bus request and second bus request signals to activate said hold request signal to request said microprocessor to relinquish control of said shared bus, said logic sequencer responsive to an active hold acknowledge signal from said microprocessor when said memory refresh circuit is maintaining an active refresh request signal to activate said refresh grant signal to grant control of said shared bus to said memory refresh circuit, said logic sequencer responsive to an active hold acknowledge signal from said microprocessor when said first and second peripheral controllers are maintaining active first and second bus request signals and said memory refresh circuit is maintaining an inactive refresh signal to activate a selected one of said first and second bus grant signals to grant control of said shared bus to a respective one of said first and second peripheral controllers, said logic sequencer arbitrating priority between said first and second bus request signals to determine which bus grant signal to activate, and said logic sequencer responsive to an active refresh request signal when said one of said first and second peripheral controllers has control of said shared bus to deactivate said selected one of first and second bus grant signals to cause said respective one of said first and second peripheral controllers to relinquish control of said shared bus and to activate said refresh grant signal to grant control of said shared bus to said memory refresh circuit, said logic sequencer further responsive to the deactivation of said refresh request signal to deactivate said refresh grant signal and to activate said selected one of said first and second bus grant signals to automatically return control of said shared bus back to said respective one of said first and second peripheral controllers without arbitrating priority between said first and second bus request signals while maintaining an active hold request signal to preclude said microprocessor from regaining control of said shared bus.