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Vertically interconnected integrated circuit chip system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/16
  • H01L-039/02
  • H01L-023/48
  • H01L-029/44
출원번호 US-0401255 (1989-08-31)
발명자 / 주소
  • Bone Robert L. (24035 Rail Cir. Laguna Niguel CA 92677) Armstrong W. E. (27571 Cenajo Mission Viego CA 92691)
인용정보 피인용 횟수 : 53  인용 특허 : 5

초록

A high density IC layout is achieved by providing conductive feedthroughs through an IC chip directly to input/output locations within the circuitry, inward from the periphery of the chip or alternately at the periphery of the chip. The chip can thus be mounted to a substrate face up, allowing for v

대표청구항

An integrated circuit (IC) assembly, comprising: (a) a substrate having an electrical interconnect circuit on one side, (b) a plurality of IC chips, each chip encompassing a substantially smaller area than the substrate and comprising: (1) a chip body having opposed sides, (2) an IC on one side of t

이 특허에 인용된 특허 (5)

  1. Nudd Graham R. (Broadway CA GB2) Marom Emanuel (Beverly Hills CA), Apparatus for high speed analysis of two-dimensional images.
  2. Grinberg Jan (Los Angeles CA) Etchells Robert D. (Topanga CA) Nudd Graham R. (Los Angeles CA) Hansen Siegfried (Los Angeles CA), Array processor architecture utilizing modular elemental processors.
  3. Narken Bernt (Poughkeepsie NY) Tummala Rao R. (Wappingers Falls NY), Multilayered glass-ceramic substrate for mounting of semiconductor device.
  4. Myer Jon H. (Woodland Hills CA) Grinberg Jan (Los Angeles CA), Parallel interconnect for planar arrays.
  5. Grinberg Jan (Los Angeles CA) Jacobson Alexander D. (Los Angeles CA) Chow Kuen (Thousand Oaks CA), Three-dimensionally structured microelectronic device.

이 특허를 인용한 특허 (53)

  1. Corisis,David J.; Moden,Walter L.; Mess,Leonard E.; Kinsman,Larry D., Assembly for stacked BGA packages.
  2. Beilin Solomon I. ; Chou William T. ; Kudzuma David ; Lee Michael G. ; Peters Michael G. ; Roman James J. ; Swamy Som S. ; Wang Wen-chou Vincent ; Moresco Larry L. ; Murase Teruo, Controlled impedance interposer substrate and method of making.
  3. Beilin Solomon I. ; Chou William T. ; Kudzuma David ; Lee Michael G. ; Peters Michael G. ; Roman James J. ; Swamy Som S. ; Wang Wen-chou Vincent ; Moresco Larry L. ; Murase Teruo, Controlled impedence interposer substrate.
  4. James M. Wark, Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  5. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  6. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  7. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  8. Akram,Salman; Gochnour,Derek J.; Hess,Michael E.; Hembree,David R., Dicing saw with variable indexing capability.
  9. Browning, Margaret; Purdom, Gregory W.; Zarling, Andrew, Hardened voyage data recorder.
  10. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  11. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  12. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  13. Akram, Salman; Brooks, Jerry M., High density modularity for IC's.
  14. Akram,Salman; Brooks,Jerry M., High-density modularity for ICS.
  15. Hawkins, Gilbert A.; Anagnostopoulos, Constantine N.; Lebens, John A., Inkjet printhead having substrate feedthroughs for accommodating conductors.
  16. Degani Yinon ; Dudderar Thomas Dixon ; Tai King Lien, Method for assembling multichip modules.
  17. Kulesza Frank W. ; Estes Richard H., Method for forming electrically conductive polymer interconnects on electrical substrates.
  18. Akram Salman ; Gochnour Derek J. ; Hess Michael E. ; Hembree David R., Method for sawing wafers employing multiple indexing techniques for multiple die dimensions.
  19. Ball,Michael B., Method of fabricating a multi-die semiconductor package assembly.
  20. Kulesza Frank W. ; Estes Richard H., Method of forming electrically conductive polymer interconnects on electrical substrates.
  21. Kulesza Frank W. ; Estes Richard H., Method of forming electrically conductive polymer interconnects on electrical substrates.
  22. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  23. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  24. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  25. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  26. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  27. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  28. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  29. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  30. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  31. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  32. Tan, Swee Seng Eric; Lee, Choon Kuan, Methods of manufacturing semiconductor device assemblies including face-to-face semiconductor dice.
  33. Haba, Belgacem; Mitchell, Craig S., Microelectronic assemblies having very fine pitch stacking.
  34. Corisis,David J.; Moden,Walter L.; Mess,Leonard E.; Kinsman,Larry D., Module assembly and method for stacked BGA packages.
  35. Corisis,David J.; Moden,Walter L.; Mess,Leonard E.; Kinsman,Larry D., Module assembly and method for stacked BGA packages.
  36. Corisis, David J.; Moden, Walter L.; Mess, Leonard E.; Kinsman, Larry D., Module assembly for stacked BGA packages.
  37. Corisis,David J.; Moden,Walter L.; Mess,Leonard E.; Kinsman,Larry D., Module assembly for stacked BGA packages.
  38. David J. Corisis ; Walter L. Moden ; Leonard E. Mess ; Larry D. Kinsman, Module assembly for stacked BGA packages with a common bus bar in the assembly.
  39. Akram, Salman, Multi-chip module substrate for use with leads-over chip type semiconductor devices.
  40. Londa Joseph Michael, Multi-electronic device package.
  41. Londa Joseph Michael, Multi-electronic device package.
  42. Horne, Craig R.; McGovern, William E.; Lynch, Robert B.; Mosso, Ronald J., Reactive deposition for electrochemical cell production.
  43. Seng, Eric Tan Swee; Kuan, Lee Choon, Semiconductor device assemblies including face-to-face semiconductor dice and related methods.
  44. Seng, Eric Tan Swee; Kuan, Lee Choon, Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies.
  45. Comer Alan E., Stacked assemblies of semiconductor packages containing programmable interconnect.
  46. Akram Salman, Stacked leads-over chip multi-chip module.
  47. Akram Salman, Stacked leads-over chip multi-chip module.
  48. Akram Salman, Stacked leads-over chip multi-chip module.
  49. Akram Salman, Stacked leads-over chip multi-chip module.
  50. Akram Salman, Stacked leads-over-chip multi-chip module.
  51. Akram Salman, Stacked leads-over-chip multi-chip module.
  52. Purdom Gregory W. ; Berecz Endre M., Stacked memory for flight recorders.
  53. Dan Kikinis, Transmitting notification of new video clips of interest from servers in wide area network.
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