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Semiconductor planarization process for submicron devices

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/469
출원번호 US-0512401 (1990-04-19)
발명자 / 주소
  • Yen Daniel L. (Chu-Tung TWX)
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Co. (Hsincho TWX 03)
인용정보 피인용 횟수 : 85  인용 특허 : 4

초록

A method is described for planarization of dielectric layers between conductor layers in multilayer metallurgy of submicron integrated circuit devices. The method begins with the integrated circuit intermediate product having devices, such as FETs or bipolar formed therein, but before interconnectio

대표청구항

Method for planarization of dielectric layers between conductor layers in multilayer metallurgy of submicron IC devices comprising: providing a semiconductor substrate having FET devices formed within and on its surface and with at least one patterned conductive layer thereover; depositing a silicon

이 특허에 인용된 특허 (4)

  1. Ting Chiu H. (Saratoga CA) Rucker Thomas G. (Palo Alto CA) Sobczak Zbigniew P. (Andover NJ), Chemical modification of spin-on glass for improved performance in IC fabrication.
  2. Anello Louis G. (Hamburg NY) Gupta Satish K. (Amherst NY) Kirtley Stephen W. (Sunnyvale CA) Wooster George S. (Hamburg NY) DePrenda Ralph L. (Amherst NY), Cyclosilazane polymers as dielectric films in integrated circuit fabrication technology.
  3. Lehrer William I. (Los Altos CA), Germanosilicate spin-on glasses.
  4. Morimoto Seiichi (Aloha OR), Semiconductor planarization process.

이 특허를 인용한 특허 (85)

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  9. Kalnitsky,Alex; Lin,Yih Shung, Enhanced planarization technique for an integrated circuit.
  10. Inoue, Yasunori; Okayama, Yoshio, Fabrication method of semiconductor device and abrasive liquid used therein.
  11. Watanabe Hiroyuki,JPX ; Mizuhara Hideki,JPX ; Saito Kimihide,JPX, Fabrication method of semiconductor device including insulation film with decomposed organic content.
  12. Choi,Byung Jin; Meissl,Mario J.; Sreenivasan,Sidlagata V.; Watts,Michael P. C., Formation of discontinuous films during an imprint lithography process.
  13. Sreenivasan, Sidlgata V.; Choi, Byung-Jin, Imprinting of partial fields at the edge of the wafer.
  14. Chang Liang-Tung,TWX ; Liao Chih-Cherng,TWX, In-situ low wafer temperature oxidized gas plasma surface treatment process.
  15. Allman, Derryl D. J.; Fuchs, Kenneth P.; Miller, Gayle W.; Gioia, Samuel C., Integrated circuit device comprising low dielectric constant material for reduced cross talk.
  16. Allman Derryl D. J. ; Fuchs Kenneth P. ; Miller Gayle W. ; Gioia Samuel C., Integrated circuit device with reduced cross talk.
  17. Allman, Derryl D. J.; Fuchs, Kenneth P.; Miller, Gayle W.; Gioia, Samuel C., Integrated circuit device with reduced cross talk.
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  19. Jin Been Yih,TWX ; Yen Daniel L. W.,TWX ; Hwang Wen Yen,TWX ; Wang Ming Hong,TWX ; Wong Sheng Hsien,TWX ; Hwang Gino,TWX ; Chang Po Shen,TWX ; Liu Yu Tsai,TWX ; Chang Chung Chi,TWX ; Yang Ta Hung,TWX, Integrated circuit passivation process and structure.
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  23. Inoue, Yasunori; Mizuhara, Hideki, Manufacturing method of semiconductor device including an insulation film on a conductive layer.
  24. Hsueh Cheng-Chen ; Lee Shih-Ked ; Lien Chuen-Der, Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit.
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  26. Hodges Robert Louis ; Nguyen Loi Ngoc, Memory masking for periphery salicidation of active regions.
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  28. Mahneke Peter,DEX, Method and apparatus for spin-coating chemicals.
  29. Ebert Andreas, Method and apparatus for temperature controlled spin-coating systems.
  30. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Method and system for double-sided patterning of substrates.
  31. Cheng,Yi Lung; Wang,Ying Lang, Method and system for fabricating a copper barrier layer with low dielectric constant and leakage current.
  32. Ben-Guigui Coren,ILX ; Levy Jeff,ILX ; Lavie Zmira,ILX, Method for depositing a flow fill layer on an integrated circuit wafer.
  33. Lavie Zmira (Zichron Yaakov ILX) Roth Aviad (Yishuv Adi ILX) Levy Jeff (Moshav Netofah ILX) Edrei Itzhak (Haifa ILX), Method for depositing a flow fill layer on an integrated circuit wafer.
  34. Wang Shih-Ming (Kaohsiung TWX), Method for improving adhesion to a spin-on-glass.
  35. Hodges, Robert Louis; Nguyen, Loi Ngoc, Method for memory masking for periphery salicidation of active regions.
  36. Chooi Simon Yew-Meng,SGX ; Zheng Jia Zhen,SGX ; Chan Lap, Method for planarizing a low dielectric constant spin-on polymer using nitride etch stop.
  37. Derryl D. J. Allman ; Kenneth P. Fuchs ; Gayle W. Miller ; Samuel C. Gioia, Method for using low dielectric constant material in integrated circuit fabrication.
  38. Sreenivasan, Sidlgata V.; McMackin, Ian M.; Melliar-Smith, Christopher Mark; Choi, Byung-Jin, Method of concurrently patterning a substrate having a plurality of fields and a plurality of alignment marks.
  39. Hodges Robert Louis ; Nguyen Loi Ngoc, Method of fabricating an integrated circuit.
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  42. Yei-Hsiung Lin TW; Chen-Bin Lin TW; Chin-Chun Huang TW, Method of manufacturing metallic interconnect.
  43. Hodges Robert Louis ; Nguyen Loi Ngoc, Method of masking for periphery salicidation of active regions.
  44. Hasper, Albert, Method of processing substrates with integrated weighing steps.
  45. Bakke,Thor; Friedrichs,Martin; V��lker,Benjamin; Haase,Thomas, Method of producing a device with a movable portion.
  46. Sreenivasan, Sidlgata V.; Watts, Michael P. C., Method to arrange features on a substrate to replicate features having minimal dimensional variability.
  47. Thakur Randhir P. S., Method to cure mobile ion contamination in semiconductor processing.
  48. Choi Ji-hyun,KRX ; Lee Hae-Jeong,KRX ; Hwang Byung-Keun,KRX ; Gou Ju-Son,KRX, Methods for forming moisture blocking layers.
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  54. Jeng Shin-Puu, Porous insulator for line-to-line capacitance reduction.
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  72. GanapathiSubramanian, Mahadevan; Choi, Byung-Jin; Miller, Michael N.; Stacey, Nicholas A., Technique for separating a mold from solidified imprinting material.
  73. Selinidis, Kosta S.; Choi, Byung-Jin; Schmid, Gerard M.; Thompson, Ecron D.; McMackin, Ian Matthew, Template having alignment marks formed of contrast material.
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