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Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with se

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/38
  • G06F-012/10
출원번호 US-0200688 (1988-05-31)
발명자 / 주소
  • Blaner Bartholomew (Newark Valley NY) Ngai Agnes Y. (Endwell NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 58  인용 특허 : 6

초록

An apparatus and method are disclosed for implementing the system architectural requirement of precise interrupt reporting in a pipelined processor with multiple functional units. Since the expense of an interrupt pipeline is warranted only for those interrupts that occur frequently-specifically, th

대표청구항

A digital computer system comprising in combination: (a) a memory; (b) an instruction processing unit (IPU) for fetching from memory and executing successive program instructions; (c) address translation lookaside buffer (TLB) means, coupled to said IPU, for converting a virtual memory address to an

이 특허에 인용된 특허 (6)

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  6. Furniss William E. (Murrysville PA) Vancsa George I. (Wexford NJ) Onufer Joseph R. (Edison NJ), Sequence of events recorder and system for transmitting sequence data from a remote station to a master station.

이 특허를 인용한 특허 (58)

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