$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Dual zone, fault tolerant computer system with error checking in I/O writes 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/16
출원번호 US-0489751 (1990-02-26)
발명자 / 주소
  • Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH)
출원인 / 주소
  • Digital Equipment Corporation (Maynard MA 02)
인용정보 피인용 횟수 : 28  인용 특허 : 17

초록

A fault tolerant computer system having a first processing system which includes a first data processor for executing a series of data processing instructions. A first data output terminal outputs data from the first processing system. A second processing system, substantially identical to the first

대표청구항

A fault tolerant computer system designed to be coupled to at least one I/O device comprising: a first processing system including a first data processor for executing a series of data processing instructions involving the passage of data into and out of said first data processor, and a first data o

이 특허에 인용된 특허 (17)

  1. Ossfeldt ; Bengt Erik, Apparatus for facilitating a cooperation between an executive computer and a reserve computer.
  2. De Bimal B. (Naperville IL) Gierut Lawrence G. (Lockport IL) Krakau Herbert B. (Elmhurst IL) Naik Kirit (Hanover Park IL) Tan-Atichat Eddie (Westmont IL), Automatic fault recovery system for a multiple processor telecommunications switching control.
  3. Censier Lucien (Conflans FR) Recoque Alice Maria (Chatenet Malabry FR), Bi-processor data handling system including automatic control of exchanges with external equipment and automatically act.
  4. Bishop Clifford F. (Cedar Rapids IA) Schultz John T. (Cedar Rapids IA), Bus stab for panelboard assembly.
  5. Joby Michael J. (Solihull GB2), Digital computing apparatus particularly for controlling a gas turbine engine.
  6. Samson Joseph E. (Dover MA) Wolff Kenneth T. (Medway MA) Reid Robert (Dunstable MA) Hendrie Gardner C. (Marlboro MA) Falkoff Daniel M. (Natick MA) Dynneson Ronald E. (Brighton MA) Clemson Daniel M. (, Digital data processor with high reliability.
  7. Strelow Horst (Cremlingen DEX), Dual-channel data processing system for railroad safety purposes.
  8. Sakata Kazuhiro (Katsuta JPX) Yuminaka Takeo (Katsuta JPX) Nakazato Masao (Katsuta JPX) Yoneda Kenji (Katsuta JPX) Kuzunuki Soshiro (Hitachi JPX) Katayama Yasunori (Hitachi JPX), Elevator control system.
  9. Beier Harley A. (Morgan Hill CA) Fukumoto Takeshi (Yokohama CA JPX) Scofield Harrison (Morgan Hill CA) Watts Vern L. (Los Gatos CA), Improving availability of a restartable staged storage data base system that uses logging facilities.
  10. Woods ; John M. ; Porter ; Marion G. ; Mills ; Donald V. ; Weller ; III ; Edward F. ; Patterson ; Garvin Wesley ; Monahan ; Earnest M., Input/output processing system utilizing locked processors.
  11. Piras Giancarlo (Milan ITX), Parallel multiprocessing system for an industrial plant.
  12. Keiles Yoel (Havertown PA), Process control system with backup process controller.
  13. Richter David L. (Plano TX), Processing system with dual buses.
  14. Long James R. (Huntsville AL) Harrill Roy L. (Walton Beach FL), Remote multiplexer terminal with redundant central processor units.
  15. Stiffler, Jack J.; Budwey, Michael J.; Nolan, Jr., James M., Self-checking computer circuitry.
  16. Giorcelli Silvano (Turin IT), System for checking two data processors operating in parallel.
  17. Davis Guy E. (Martinez CA), System for manually or automatically transferring control between computers without power generation disturbance in an e.

이 특허를 인용한 특허 (28)

  1. Long,Finbarr Denis; Ardini,Joseph; Kirkpatrick,Dana A.; O'Keeffe,Michael James, Apparatus and methods for fault-tolerant computing using a switching fabric.
  2. Sonnier David Paul ; Baker William Edward ; Bunton William Patterson ; Krause John C. ; Porter Kenneth H. ; Watson William Joel ; Zalzala Linda Ellen, Apparatus for detecting divergence between a pair of duplexed, synchronized processor elements.
  3. Takehara, Jun; Aramaki, Naruhiko; Kawamura, Toshikazu; Sameda, Yoshito; Nakatani, Hiroshi; Okabe, Motohiko; Yoshida, Yukitaka, Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line.
  4. Meyers Steven C. (Round Rock TX) Brown John Michael (Austin TX) Bruckert William F. (Austin TX) Klecka James Stephens (Lexington TX), Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator produ.
  5. Torbjrnsen ystein (Trondheim NOX) Hvasshovd Svein-Olaf (Trondheim NOX), Continuously available database server having multiple groups of nodes with minimum intersecting sets of database fragme.
  6. Baleani, Massimo; Losi, Marco; Ferrari, Alberto; Mangeruca, Leonardo, Electronic system for detecting a fault.
  7. Zizzi,Stephen, Encrypting file system.
  8. Ohguro Hiroshi,JPX ; Ikeda Koichi,JPX ; Nishiyama Takaaki,JPX ; Iwamoto Hiroshi,JPX ; Kurosawa Kenichi,JPX ; Nakamikawa Tetsuaki,JPX ; Morioka Michio,JPX, Fault recovering system provided in highly reliable computer system having duplicated processors.
  9. Bissett Thomas D. ; Fitzgerald ; V Martin J. ; Leveille Paul A. ; McCollum James D. ; Muench Erik ; Tremblay Glenn A., Fault resilient/fault tolerant computing.
  10. Bissett Thomas D. ; Fitzgerald ; V Martin J. ; Leveille Paul A. ; McCollum James D. ; Muench Erik ; Tremblay Glenn A., Fault resilient/fault tolerant computing.
  11. Bissett Thomas Dale ; Fiorentino Richard D. ; Glorioso Robert M. ; McCauley Diane T. ; McCollum James D. ; Tremblay Glenn A. ; Troiani Mario, Fault resilient/fault tolerant computing.
  12. Bissett Thomas Dale ; Fiorentino Richard D. ; Glorioso Robert M. ; McCauley Diane T. ; McCollum James D. ; Tremblay Glenn A. ; Troiani Mario, Fault resilient/fault tolerant computing.
  13. Mikael Ronstrom SE, Fault tolerant computer system.
  14. Somers, Jeffrey S.; Huang, Wen-Yi; Tetreault, Mark D.; Wegner, Timothy M., Fault-tolerant computer system with voter delay buffer.
  15. Suffin, A. Charles; Amato, Joseph S.; Joyce, Paul, Fault-tolerant maintenance bus architecture.
  16. Suffin, A. Charles, Fault-tolerant maintenance bus protocol and method for using the same.
  17. Shimomura Tetsuya,JPX ; Murabayashi Fumio,JPX ; Shimamura Kotaro,JPX ; Kanekawa Nobuyasu,JPX ; Hotta Takashi,JPX, Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them.
  18. Tetsuya Shimomura JP; Fumio Murabayashi JP; Kotaro Shimamura JP; Nobuyasu Kanekawa JP; Takashi Hotta JP, Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them.
  19. Nayyar, Jasbir Singh; Nuthakki, Shashank Srinivasa; Gulati, Rahul; Shrimali, Arun, Integrated circuit chip with cores asymmetrically oriented with respect to each other.
  20. Somers, Jeffrey S.; Tetreault, Mark D.; Wegner, Timothy M., Method and system for upgrading fault-tolerant systems.
  21. Thurman Audree (Phoenix AZ) Person Stan (Mesa AZ) Norden-Paul Ronald (Mesa AZ) Shelton Richard (Mesa AZ), Method for processing and storing a transaction in a distributed database system.
  22. Essame, Didier; Forin, Philippe; Fumery, Benoit, Method for verifying redundancy of secure systems.
  23. Matsuda Koji,JPX ; Miyazaki Yoshihiro,JPX ; Takaya Soichi,JPX ; Hyuga Kazuhiro,JPX ; Akeura Nobuo,JPX ; Yamaguchi Shinichiro,JPX ; Miyazaki Naoto,JPX ; Kayukawa Satoru,JPX, Method of and system for verifying operation concurrence in maintenance/replacement of twin CPUs.
  24. Horst Robert W. ; Garcia David J. ; Bunton William Patterson ; Bruckert William F. ; Fowler Daniel L. ; Jones ; Jr. Curtis Willard ; Sonnier David Paul ; Watson William Joel ; Williams Frank A., Self-checked, lock step processor pairs.
  25. Takeuchi, Ken; Tanakamaru, Shuhei, Semiconductor storage device and control method for same.
  26. Khosravi,Hormuzd M., Stateless redundancy in a network device.
  27. Nelvin, Robert E.; Tetreault, Mark D.; Alden, Andrew; Dolaty, Mohsen; Edwards, Jr., John W.; Kement, Michael W.; MacLeod, John R., System and method for operating a system with redundant peripheral bus controllers.
  28. Beardsley Brent Cameron (Tucson AZ) Knowlden Ronald Robert (Tucson AZ) Spear Gail Andrea (Tucson AZ), Use of configuration registers to control access to multiple caches and nonvolatile stores.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로