초록 ▼

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconn

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and hose wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment and the passivation covering of the assembly are disclosed.

대표청구항 ▼

The method of fabricating a wafer scale integration multiple die integrated circuit comprising the steps of: etching die receptacle wells into the planar top surface of a polished oxide coated semiconductor wafer, said receptacle wells each having a bottom area, sloping sidewall surfaces and rim por

The method of fabricating a wafer scale integration multiple die integrated circuit comprising the steps of: etching die receptacle wells into the planar top surface of a polished oxide coated semiconductor wafer, said receptacle wells each having a bottom area, sloping sidewall surfaces and rim portions; depositing uncured liquid adhesive material in the bottom area of each said receptacle well; inserting integrated circuit die having top, sidewall, and backside surfaces into said receptacle wells and said uncured adhesive resident therein to form a wafer and die assembly: rotating said wafer and inserted die assembly into an inverted, top surface down, position wherein said liquid adhesive material is resident around said sidewall and backside surfaces of each said die; aligning the inverted top surfaces of said die and wafer into a planar condition wherein the inverted die top surface and wafer top surface rest against a flat planar tooling member; and applying adhesive flow promoting and cure promoting elevated temperature to the inverted wafer and die assembly to encourage adhesive flow downward into the space between die sidewall and receptacle well sidewall surfaces, and the curing of said adhesive into a solidified mass conforming with the die and receptacle well surfaces and with the surface of said flat planar tooling member.