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Thermal protection method for a power device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/36
출원번호 US-0438382 (1989-11-20)
발명자 / 주소
  • Davies Robert B. (Tempe AZ) Jarrett Robert B. (Tempe AZ)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 50  인용 특허 : 10

초록

A thermally protected power transistor comprising a first chip which includes a power transistor and a second chip which includes protection circuitry. The second chip has a plurality of metallic bumps formed thereon which are coupled to various portions of the protection circuitry, wherein at least

대표청구항

A thermally protected switch comprising: a first chip having the switch formed thereon and having an electrode wherein the switch is on when a control signal is present on the electrode; and a second chip having control circuitry formed on a top side, the control circuitry further comprising a tempe

이 특허에 인용된 특허 (10)

  1. Satoh Ryohei (Yokohama JPX) Oshima Muneo (Yokohama JPX) Tanaka Minoru (Yokohama JPX) Sakaguchi Suguru (Chigasaki JPX) Murata Akira (Tokyo JPX) Hirota Kazuo (Chigasaki JPX), Electronic circuit device and method of producing the same.
  2. Tihanyi Jenoe (Munich DEX) Bierlmaier Johann (Munich DEX), MOSFET with temperature protection.
  3. Hasegawa Hitoshi (Tama JPX), Method for producing a semiconductor device.
  4. Pammer Erich (Taufkirchen DEX) Bischofberger Otfried (Munich DEX), Method for the galvanic manufacture of metallic bump-like lead contacts.
  5. Nakata Josuke (Itami JPX) Kameda Tohru (Itami JPX), Semiconductor device with a thermal protective device.
  6. Sawai Masaaki (Takasaki JPX), Semiconductor laser module having an improved temperature control arrangement.
  7. Schelhorn, Robert L., Structure for mounting a semiconductor chip to a metal core substrate.
  8. Yoshikawa Shoji (Tokyo JPX), Temperature control device for a semiconductor laser.
  9. Watanabe Hideo (Kanagawa JPX), Temperature controller for semiconductor device.
  10. Jenkins James O. M. (Swansea GBX), Temperature sensing apparatus.

이 특허를 인용한 특허 (50)

  1. Nobutaka Nishigaki JP, Apparatus for controlling internal heat generating circuit.
  2. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Assembly of electronic components.
  3. Martinez Roberto ; Cheah Chuan, Co-packaged MOS-gated device and control integrated circuit.
  4. Gronwald, Frank; Lietz, Franz-Josef, Coated motor vehicle battery sensor element and method for producing a motor vehicle battery sensor element.
  5. James M. Wark, Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  6. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  7. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  8. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  9. Otremba,Ralf, Electronic component and method for its assembly.
  10. Williams, Susan; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Electronic component with wire bonds in low modulus fill encapsulant.
  11. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Electronic device with wire bonds adhered between integrated circuits dies and printed circuit boards.
  12. Pricer Wilbur ; Goodnow Kenneth Joseph ; Michail Michel S. ; Patel Janak Ghanshyambhai ; Ventrone Sebastian T., Integrated hot spot detector for design, analysis, and control.
  13. Zommer Nathan, Isolated multi-chip devices.
  14. Qualich John R., Loss-less load current sensing driver and method therefor.
  15. Nishigaki,Nobutaka; Ninomiya,Ryoji; Sakai,Makoto, Method and apparatus for controlling internal heat generating circuit.
  16. Duvvury Charvaka, Method and system for protecting integrated circuits against a variety of transients.
  17. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Method of adhering wire bond loops to reduce loop height.
  18. Chung Long Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Method of applying encapsulant to wire bonds.
  19. Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Method of encapsulating wire bonds.
  20. Ball,Michael B., Method of fabricating a multi-die semiconductor package assembly.
  21. Mongan Ryan H., Method of junction temperature determination and control utilizing heat flow.
  22. Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Method of wire bond encapsulation profiling.
  23. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Method of wire bonding an integrated circuit die and a printed circuit board.
  24. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  25. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  26. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  27. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  28. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  29. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  30. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  31. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  32. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  33. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  34. Brown, David R, Modular orthopedic implant.
  35. Brauchle Peter (Nehren DEX) Uebele Manfred (Reutlingen DEX), Monolithically integrated mos output-stage component having an excess-temperature protection device.
  36. Davies, Robert Bruce, Power semiconductor device and method therefor.
  37. Davies, Robert Bruce, Power semiconductor device and method therefor.
  38. Davies, Robert Bruce, Power semiconductor device and method therefor.
  39. Davies, Robert Bruce, Power semiconductor device and method therefor.
  40. Davies, Robert Bruce, Power semiconductor device and method therefor.
  41. Moline, Dan, RF power transistor having an encapsulated chip package.
  42. Davies, Robert Bruce, Radio frequency power semiconductor device comprising matrix of cavities as dielectric isolation structure.
  43. Moline, Daniel D., Semiconductor component.
  44. Pavio,Jeanne S., Semiconductor component and method of manufacture.
  45. Guo,Sam Y, Solid state switch with quasi-predictive short circuit protection and thermal protection.
  46. Torrisi, Giovanni Luca; Porto, Domenico Massimo; Lecce, Sergio; Gaertner, Manuel, Thermal control process for a multi-junction electronic power device and corresponding electronic power device.
  47. Porto, Domenico Massimo; Torrisi, Giovanni Luca; Gaertner, Manuel; Lecce, Sergio, Thermal control process for a multijunction electronic power device and corresponding electronic power device.
  48. Lee, Min-Woo; Jang, Kyung-Oun; Cho, Dae-Woong, Thermal shutdown unit, switch controller including the same, and control method of thermal shutdown protection operation.
  49. Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Wire bond encapsulant application control.
  50. Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Wire bond encapsulant control method.
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