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Method of cooling and powering an integrated circuit chip using a compliant interposing pad

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/60
  • H01L-021/54
  • H01L-021/58
출원번호 US-0549611 (1990-07-09)
발명자 / 주소
  • Fox Leslie R. (Boxborough MA) Wade Paul C. (Shirley MA) Schmidt William L. (Acton MA)
출원인 / 주소
  • Digital Equipment Corp. (Maynard MA 02)
인용정보 피인용 횟수 : 38  인용 특허 : 6

초록

An IC chip assembly includes a chip having an array of exposed contacts at a first face thereof, a substrate having an array of exposed contacts at a face thereof and a compliant interposer with exposed contacts at opposite faces thereof positioned between the chip and substrate so that contacts on

대표청구항

The method of connecting and cooling an IC chip comprising the steps of: forming a compliant pad with an array of electrical conductors embedded in said pad with the opposite ends of the conductors being exposed at opposite faces of the pad; sandwiching the compliant pad between a chip and a substra

이 특허에 인용된 특허 (6)

  1. Werbizky George G. (Vestal NY), Circuit module with separate signal and power connectors.
  2. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  3. Neugebauer Constantine A. (Schenectady NY), Hybrid integrated circuit chip package.
  4. Demnianiuk, Eugene F., Levered system connector for an integrated circuit package.
  5. Nitta Mitsuru (Tokyo JPX) Inoue Tatsuo (Tokyo JPX), Mounting structure for a chip.
  6. Butt Sheldon H. (Godfrey IL), Tape packages.

이 특허를 인용한 특허 (38)

  1. Akagawa Masatoshi,JPX, Anisotropic conductive sheet and printed circuit board.
  2. Naoi Masaya,JPX, Anisotropic conductivity sheet with positioning portion.
  3. McCormick,Carolyn; Jessep,Rebecca; Dungan,John; Boggs,David W.; Sato,Daryl, Arrangement of vias in a substrate to support a ball grid array.
  4. Chiu Anthony M., Ball contact for flip-chip device.
  5. Chiu Anthony M., Ball contact for flip-chip devices.
  6. Distefano Thomas H., Bonding lead structure with enhanced encapsulation.
  7. Blanquart, Laurent; Richardson, John, Camera system with minimal area monolithic CMOS image sensor.
  8. Blanquart, Laurent; Richardson, John, Camera system with minimal area monolithic CMOS image sensor.
  9. Martin,Robert A., Chip mount, methods of making same and methods for mounting chips thereon.
  10. Lo, Ching P.; Huang, Daniel A.; Hudson, Pete, Chip scale packaging on CTE matched printed wiring boards.
  11. Lo, Ching P.; Huang, Daniel A.; Hudson, Pete, Chip scale packaging on CTE matched printed wiring boards.
  12. Cheng, Chih-Min; Collins, Andrew, Electronic device containing thermal interface material.
  13. Stansbury Darryl M., Field emission display with multi-level interconnect.
  14. Blanquart, Laurent; Talbert, Joshua D.; Henley, Jeremiah D.; Wichern, Donald M., Image sensor for endoscopic use.
  15. Blanquart, Laurent; Talbert, Joshua D.; Henley, Jeremiah D.; Wichern, Donald M., Image sensor for endoscopic use.
  16. Blanquart, Laurent; Talbert, Joshua D.; Henley, Jeremiah D.; Wichern, Donald M., Image sensor for endoscopic use.
  17. Blanquart, Laurent, Image sensor with tolerance optimizing interconnects.
  18. Blanquart, Laurent, Image sensor with tolerance optimizing interconnects.
  19. Bambridge, Timothy Brooks; Gilbert, Jeffery J.; Herbsommer, Juan Alejandro; Klemovage, Jeffrey Michael; Libricz, Jr., George John, Integrated circuit device having flexible leadframe.
  20. Bambridge,Timothy Brooks; Gilbert,Jeffery J.; Herbsommer,Juan Alejandro; Klemovage,Jeffrey Michael; Libricz, Jr.,George John, Integrated circuit device having flexible leadframe.
  21. Jones Tim (Chandler AZ) Ommen Denise (Phoenix AZ) Baird John (Scottsdale AZ), Low-profile ball-grid array semiconductor package and method.
  22. Durand David (Providence RI) Wong Chon M. (Lincoln RI) Iannetta ; Jr. Roger A. (Warwick RI), Method for connecting a die to electrically conductive traces on a flexible lead-frame.
  23. Mok Sammy L. (Cupertino CA), Mounting assembly for multiple chip module with more than one substrate and computer using same.
  24. Stansbury Darryl M., Multi-layer electrical interconnection structures.
  25. Stansbury Darryl M. (Boise ID), Multi-layer electrical interconnection structures and fabrication methods.
  26. Mok Sammy L., Multiple chip module assembly for top of mother board.
  27. Mok Sammy L. (Cupertino CA), Multiple chip module mounting assembly and computer using same.
  28. Blanquart, Laurent, Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects.
  29. Blanquart, Laurent, Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects.
  30. Chia Chok J. ; Lim Seng Sooi ; Variot Patrick, Process for using a removeable plating bus layer for high density substrates.
  31. Khandros,Igor Y.; DiStefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
  32. Waki Masaki,JPX, Semiconductor device having tab-leads and a fabrication method thereof.
  33. Talbert, Joshua D.; Henley, Jeremiah D.; Wichern, Donald M.; Wichern, Curtis L., System and method for providing a single use imaging device for medical applications.
  34. Blanquart, Laurent, System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects.
  35. Talbert, Joshua D.; Henley, Jeremiah D.; Wichern, Donald M., System, apparatus and methods for providing a single use imaging device for sterile environments.
  36. Petersen Kurt H., Top load socket for ball grid array devices.
  37. Caletka, David Vincent; Park, Seungbae; Sathe, Sanjeev Balwant, Wafer scale thin film package.
  38. Caletka,David Vincent; Park,Seungbae; Sathe,Sanjeev Balwant, Wafer scale thin film package.
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