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A semiconductor integrated circuit device enabled to perform both a normal writing operation using a voltage elevated with the internal supply voltage taken as the reference voltage and a writing operation with the use of another voltage elevated with an external voltage applied to an external termi

A semiconductor integrated circuit device enabled to perform both a normal writing operation using a voltage elevated with the internal supply voltage taken as the reference voltage and a writing operation with the use of another voltage elevated with an external voltage applied to an external terminal taken as the reference voltage, whereby margin measurement, high-voltage test, and accelerated test are enabled to be performed even after packaging. Further, by providing the apparatus with a mode selector having a plurality of latch circuits operating at different timing connected to an input terminal so that modes are switched by changing combination of the signals latched in such latch circuits, the number of operating modes can be increased without increasing the number of pins.

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A semiconductor memory device including a plurality of nonvolatile storage elements each of which requires a predetermined voltage to write a data into a nonvolatile storage element, a first external terminal for receiving an external writing control signal and a second external terminal for receivi

A semiconductor memory device including a plurality of nonvolatile storage elements each of which requires a predetermined voltage to write a data into a nonvolatile storage element, a first external terminal for receiving an external writing control signal and a second external terminal for receiving an external output control signal for controlling output of a stored data in a nonvolatile storage element, said semiconductor memory device comprising: voltage generating means for generating a first voltage; voltage limiting means coupled to said voltage generating means and including an internal reference node and means for limiting said first voltage to a limited voltage in accordance with a second voltage applied to said internal reference node; external voltage providing means coupled to said first external terminal and to said internal reference node, and including means for providing an internal voltage corresponding to an external voltage applied to said second external terminal to said internal reference node; switching means coupled to said internal reference node and to mode selection means and responsive to a mode selection signal from said mode selection means for providing a reference voltage to said internal reference node so that said limited voltage becomes substantially equal to said predetermined voltage, wherein said switching means allows said limited voltage to change to a voltage having smaller absolute value than that of said predetermined voltage in accordance with said external voltage in a state which said switching means does not provide said reference voltage to said internal reference node; and said mode selection means including: timing signal generating means coupled to said first external terminal, and including means responsive to a change from a first level to a second level in a control signal to be applied to said first external terminal for generating a first operation signal and means responsive to a change from said second level to said first level in said control signal for generating a second operation signal; first holding means coupled to said second external terminal and responsive to said first operation signal for holding data applied on said second external terminal; second holding means coupled to said second external terminal and responsive to said second operations signal for holding data applied on said second external terminal; and mode select circuit coupled to said first and second holding means and for generating said mode selection signal in accordance with the held data in said first and second holding means.