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Quad processor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/306
  • B44C-001/22
출원번호 US-0443039 (1989-12-01)
발명자 / 주소
  • Maher Joseph A. (South Hamilton MA) Vowles E. John (Goffstown NH) Napoli Joseph D. (Winham NH) Zafiropoulo Arthur W. (Manchester MA) Miller Mark W. (Burlington MA)
출원인 / 주소
  • General Signal Corporation (Stamford CT 02)
인용정보 피인용 횟수 : 24  인용 특허 : 32

초록

The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the several plasma vessels and the wafer queuing station witho

대표청구항

A multiple-processing and contamination-free wafer handling and processing system, comprising: plural, wafer receiving and surface processing vessels each having an ingress and egress defining port that are arrayed about a predetermined spacial locus in such a way that the several ports thereof are

이 특허에 인용된 특허 (32)

  1. Prentakis Antonios E. (Cambridge MA), Apparatus and method for loading and unloading wafers.
  2. Foster Robert (San Francisco CA) Wang David N. (Cupertino CA) Somekh Sasson (Redwood City CA) Maydan Dan (Los Altos Hills CA), Apparatus and method for magnetron-enhanced plasma-assisted chemical vapor deposition.
  3. Mintz Donald M. (Sunnyvale CA), Apparatus and method for manufacturing planarized aluminum films.
  4. Richards Edmond A. (Marlton NJ), Apparatus for conveying a semiconductor wafer.
  5. Bok Edward (Burg. Amersfoordtlaan 82 1171 DR Badhoevedorp NLX), Apparatus for floating transport and processing of substrate or tape.
  6. Kamohara Hideaki (Ibaraki JPX) Fujioka Kazumasa (Ibaraki JPX) Kobari Toshiaki (Ibaraki JPX) Takahashi Kunihiro (Ibaraki JPX) Ueda Shinjiro (Abiko JPX), Apparatus for manufacturing semiconductors.
  7. Sato, Kazuo; Yamaguchi, Sumio; Kato, Shigeo; Matsumura, Yasuhide; Mizumoto, Muneo; Okuno, Sumio; Tamura, Naoyuki, Apparatus for molecular beam epitaxy.
  8. Tateishi Hideki (Yokohama JPX) Kamei Tsuneaki (Kanagawa JPX) Abe Katsuo (Yokosuka JPX) Kobayashi Shigeru (Kawasaki JPX) Aiuchi Susumu (Yokohama JPX) Nakatsukasa Masashi (Tama JPX) Takahashi Nobuyuki , Apparatus for performing continuous treatment in vacuum.
  9. Gallego JosM. (Ormskirk GB2), Apparatus for the deposition of multi-layer coatings.
  10. Uehara, Akira; Hijikata, Isamu; Nakane, Hisashi; Nakayama, Muneo, Automatic plasma processing device and heat treatment device.
  11. Hutchinson Martin A. (Santa Clara CA), Gate valve for wafer processing system.
  12. Bouchaib Pierre (L\Etang la Ville FRX), Installation for treatment of materials for the production of semi-conductors.
  13. Ackley James W. (Los Altos CA), Load lock pumping mechanism.
  14. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Cheng Mei (San Jose CA) Cheng David (San Jose CA), Magnetron-enhanced plasma etching process.
  15. Shibata Fumio (Kudamatsu JPX) Nagatomo Katsuaki (Kudamatsu JPX) Fukuhara Hidetomo (Kudamatsu JPX) Marumoto Gen (Kudamatsu JPX) Okudaira Sadayuki (Oume JPX), Method and apparatus for plasma process.
  16. Hugues Jean B. (Tempe AZ) Weber Lynn (Saratoga CA) Herlinger James E. (Palo Alto CA) Nishikawa Katsuhito (San Jose CA) Schuman Donald L. (Saratoga CA) Yee Gary W. (Santa Clara CA), Method and apparatus for transferring wafers between cassettes and a boat.
  17. Rubin Richard H. (Fairfield NJ) Petrone Benjamin J. (Netcong NJ) Heim Richard C. (Mountain View CA) Pawenski Scott M. (Wappingers Falls NY), Modular processing apparatus for processing semiconductor wafers.
  18. Bok Edward (Badhoevedorp NLX), Module for high vacuum processing.
  19. Hockersmith Dan T. (Garland TX) Gilbert Joe W. (Leonard TX), Plasma etch movable substrate.
  20. Warenback, Douglas H.; Rathmann, Thomas M.; Mirkovich, Ninko T., Plasma reactor chuck assembly.
  21. Mimura Takashi (Machida JPX) Hikosaka Kohki (Yokohama JPX) Odani Kouichiro (Sagamihara JPX), Process and apparatus for fabricating a semiconductor device.
  22. Maher Joseph A. (South Hamilton MA) Vowles E. John (Goffstown NH) Napoli Joseph D. (Winham NH) Zafiropoulo Arthur W. (Manchester MA) Miller Mark W. (Burlington MA), Quad processor.
  23. Hutchinson Martin A. (Santa Clara CA), Sputter module for modular wafer processing machine.
  24. Messer Mark G. (Los Gatos CA) Stark Lawrence R. (San Jose CA), Sputter module for modular wafer processing system.
  25. Takahashi Nobuyuki (Fuchu JPX) Kitahara Hiroaki (Fuchu JPX), Substrate processing apparatus.
  26. Takahashi Nobuyuki (Tokyo JPX), Substrate processing apparatus.
  27. Strahl Thomas L. (Fremont CA) Lamont ; Jr. Lawrence T. (San Jose CA) Peterson Carl T. (Fremont CA) Brown Hobart A. (Santa Cruz CA) McCormick Lonnie W. (Cupertino CA) Mosely Roderick C. (Mountain View, System and method for processing workpieces.
  28. Layman Frederick P. (Fremont CA) Kuhlman Michael J. (Fremont CA), System for measuring the position of a wafer in a cassette.
  29. Madan Arun (Golden CO) Von Roedern Bolko (Wheat Ridge CO), Thin film deposition apparatus including a vacuum transport mechanism.
  30. Hutchinson, Martin A.; Shaw, R. Howard; Coad, George, Transfer plate rotation system.
  31. Hobson Phillip M. (Los Altos CA) Dick Paul H. (San Jose CA), Wafer processing chuck using slanted clamping pins.
  32. Layman Frederick P. (Fremont CA) Huntley David A. (Mountain View CA) Dick Paul H. (San Jose CA) Coad George L. (Lafayette CA) Kuhlman Michael J. (Fremont CA) Vecta Roger M. (San Jose CA) Hobson Phill, Wafer processing system.

이 특허를 인용한 특허 (24)

  1. Ihantola Heikki,FIX, Apparatus and method for processing of semiconductors, such as silicon chips.
  2. Maeda Kazuo (Tokyo JPX) Ohira Kouichi (Tokyo JPX) Chino Hiroshi (Tokyo JPX), Apparatus for manufacturing semiconductor device.
  3. Glants Alex, Automatic positive pressure seal access door.
  4. Nguyen Thu Q. ; Phu Hung Q., Flexible placement of GTL end points using double termination points.
  5. Moschini Lawrence R., Hybrid heater with ceramic foil serrated plate and gas assist.
  6. Felsenthal David ; Lee Chunghsin ; Sferlazzo Piero, In-line sputter deposition system.
  7. Joseph A. Maher ; E. John Vowles ; Joseph D. Napoli ; Arthur W. Zafiropoulo ; Mark W. Miller, Integrated processing system having multiple reactors connected to a central chamber.
  8. Maher, Joseph A.; Vowles, E. John; Napoli, Joseph D.; Zafiropoulo, Arthur W.; Miller, Mark W., Integrated processing system having multiple reactors connected to a central chamber.
  9. Kawamura Yoshio,JPX ; Yamamoto Tatuharu,JPX ; Moriyama Shigeo,JPX ; Kawamoto Yoshifumi,JPX ; Yokoyama Natsuki,JPX ; Uchida Fumihiko,JPX ; Hidaka Minoru,JPX ; Matsui Miyako,JPX, Method and apparatus for fabricating semiconductor devices.
  10. Felsenthal David ; Lee Chunghsin ; Sferlazzo Piero, Multi-layer sputter deposition apparatus.
  11. Matsuse Kimihiro,JPX, Processing apparatus and processing system.
  12. Tepolt Gary B., Robotic wafer handler.
  13. Muka Richard S., Substrate heating apparatus with cantilevered lifting arm.
  14. Beaulieu David ; Pippins Michael W., Substrate processing apparatus having a substrate transport with a front end extension and an internal substrate buffer.
  15. Adams Douglas R., Substrate processing apparatus with small batch load lock.
  16. Klein, Martin P.; Felsenthal, David; Sferlazzo, Piero, Substrate processing pallet and related substrate processing method and machine.
  17. Klein, Martin P.; Felsenthal, David; Sferlazzo, Piero, Substrate processing pallet and related substrate processing method and machine.
  18. Klein, Martin P.; Felsenthal, David; Sferlazzo, Piero, Substrate processing pallet and related substrate processing method and machine.
  19. Maher Joseph A. ; Vowles E. John ; Napoli Joseph D. ; Zafiropoulo Arthur W. ; Miller Mark W., System for processing substrates.
  20. Klein,Martin P.; Keigler,Arthur; Felsenthal,David, Ultra-thin wafer handling system.
  21. Maher Joseph A. ; Vowles E. John ; Napoli Joseph D. ; Zafiropoulo Arthur W. ; Miller Mark W., Vacuum substrate processing system having multiple processing chambers and a central load/unload chamber.
  22. Toshima Masato, Wafer transfer system and method of using the same.
  23. Toshima Masato, Wafer transfer system and method of using the same.
  24. Kawamura Yoshio (Kokubunji-ken JPX) Kawamoto Yoshifumi (Kanagawa JPX) Uchida Fumihiko (Hachioji JPX) Mizuishi Kenichi (Hachioji JPX) Yokoyama Natsuki (Mitaka JPX) Murakami Eiichi (Tokorozawa JPX) Nak, Wafer transport method.
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