초록 ▼

A computing system for a flight simulator is formed as a distributed system with a common bus MFB to which five processing modules 11 to 15 are connected. The module 11 processes data relating to aircraft movement and receives data from a pilot\s manual controls simulator 16, and supplies data to a

A computing system for a flight simulator is formed as a distributed system with a common bus MFB to which five processing modules 11 to 15 are connected. The module 11 processes data relating to aircraft movement and receives data from a pilot\s manual controls simulator 16, and supplies data to a motion output unit 17 and a visual field output unit 18. the module 12 processes data relating to engine performance. The module 13 processes data relating to navigation and communciations, and the module 14 processes data relating to aircraft equipment systems such as hydraulic and electrical systems. The modules 12, 13 and 14 may each supply control signals to instruments read by a trainee pilot, and each receive signals from manually operable members or switches operated by the trainee pilot. The module 15 is an instructor station and communicates with a VDU terminal 21. Each module contains, in an interface circuit MFI, a memory which stores data shared by all five modules, the memory being organized so that each module can read any of the data but can only write into a respective allocated region of the memory. The interface circuits MFI each broadcast the contents of their respective allocated memory regions in a predetermined order during a short period at the beginning of each computing frame. Each MFI thus receives the updated contents of the regions allocated to the other MFIs and has an address generator which ensures that the updated contents are written into the correct regions of the memory. Local area networks ML and DL couple the modules 11 to 15 to a management computer MC for program loading and debugging.

대표청구항 ▼

A computing system comprising a common bus, a plurality of processing units coupled to said common bus, and means for generating a start signal at times separated by regular intervals, each of said units including a memory means organized into regions allocated to the plurality of processing units f

A computing system comprising a common bus, a plurality of processing units coupled to said common bus, and means for generating a start signal at times separated by regular intervals, each of said units including a memory means organized into regions allocated to the plurality of processing units for storing data processed by the plurality of units, means for reading the data in the region allocated to that unit and in at least one other region, means for writing data updated by the activity of that unit into the region allocated to that unit and into no other region, means for placing on said bus data stored in the region allocated to that unit, and means for writing data placed on the bus by the other units into the other regions, each processing unit being adapted to carry out predetermined operations during each of said regular intervals, said operations including writing data placed on said bus by the respective other units into said other allocated regions, and placing the data stored in the region allocated to that unit on said bus and wherein at least one of the units includes means for causing during a portion of each of said regular intervals each of the units in succession to place on said bus the data written into the respective allocated region during the previous one of said regular intervals.