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High density interconnect with high volumetric efficiency 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/11
출원번호 US-0250010 (1988-09-27)
발명자 / 주소
  • Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY)
출원인 / 주소
  • General Electric Company (Schenectady NY 02)
인용정보 피인용 횟수 : 59  인용 특허 : 8

초록

Interconnected integrated circuits (16) packaged at a very high density are fabricated beginning with a plurality of substrates (50 or 400 or 500) where each substrate has metal edge contact sites (12 or 507). Several substrates are joined together in a stack (82 or 402 or 512) held together tightly

대표청구항

A stack of interconnected integrated circuits, comprising: a plurality of substrates in a stacked configuration, each of said substrates having an integrated circuit positioned thereof, respectively; electrical connecting means on each of said substrates, respectively, for providing electrical conne

이 특허에 인용된 특허 (8)

  1. Alvarez Juan M. (Medfield MA) Breit Henry F. (Attleboro MA) Levy Steven E. (Plainville MA) Hingorany Premkumar R. (Foxboro MA), Heat dissipating member for mounting a semiconductor device and electrical circuit unit incorporating the member.
  2. Elarde Vito D. (San Diego CA), Method of manufacturing injection molded printed circuit boards in a common planar array.
  3. Nakano Tsuyoshi (Tokyo JPX), Method of stacking printed circuit boards.
  4. Tracy John M. (Thousand Oaks CA), Modulator multilayer detector.
  5. Smolley Robert (Porteughese Bend CA), Multi-element circuit construction.
  6. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY), Multichip integrated circuit packaging configuration and method.
  7. Peterson Robert K. (Garland TX) Mowatt Larry J. (Allen TX) Poteet Aaron D. (Austin TX), Thermal interface for a printed wiring board.
  8. Woodman John K. (601 Mystic La. Foster City CA 94404), Three dimensional integrated circuit package.

이 특허를 인용한 특허 (59)

  1. Vinciarelli,Patrizio; Briere,Michael; Dumas,Jeffrey Gordon, Active filtering.
  2. Robert John Wojnarowski ; Glenn Alan Forman ; Yung Sheng Liu, Alignment of optical interfaces for data communication.
  3. Wojnarowski Robert John ; Forman Glenn Alan ; Liu Yung Sheng, Alignment of optical interfaces for data communication.
  4. Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Apparatus for circuit encapsulation.
  5. John R. Saxelby, Jr. ; Walter R. Hedlund, III, Circuit encapsulation.
  6. Saxelby, Jr., John R.; Hedlund, III, Walter R., Circuit encapsulation.
  7. Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Circuit encapsulation process.
  8. Vinciarelli,Patrizio; Prager,Jay, Components having actively controlled circuit elements.
  9. Gorowitz Bernard ; Wojnarowski Robert John ; Kolc Ronald Frank, Demountable and repairable low pitch interconnect for stacked multichip modules.
  10. Wright, Jason R.; Vincent, Michael B.; Yap, Weng F., Devices and stacked microelectronic packages with in-trench package surface conductors and methods of their fabrication.
  11. Vincent, Michael B.; Wright, Jason R.; Yap, Weng F., Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication.
  12. Vincent, Michael B.; Hayes, Scott M., Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication.
  13. Vincent, Michael B.; Hayes, Scott M., Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication.
  14. Vincent, Michael B.; Gong, Zhiwei, Devices and stacked microelectronic packages with parallel conductors and intra-conductor isolator structures and methods of their fabrication.
  15. Saxelby ; Jr. John R. ; Johnson Brant T., Direct metal bonding.
  16. Saxelby ; Jr. John R. ; Johnson Brant T., Direct metal bonding.
  17. Fjelstad,Joseph C.; Segaram,Para K.; Haba,Belgacem, Direct-connect integrated circuit signaling system for bypassing intra-substrate printed circuit signal paths.
  18. Fjelstad, Joseph C.; Segaram, Para K.; Haba, Belgacem, Direct-connect signaling system.
  19. Japp, Robert M.; Kevern, Gregory A.; Poch, Francis S., Drill stack formation.
  20. Japp,Robert M.; Kevern,Gregory A.; Poch,Francis S., Drill stack formation.
  21. Ead George J., Flowing solder in a gap.
  22. Fjelstad, Joseph C.; Grundy, Kevin P.; Yasumura, Gary, IC package structures having separate circuit interconnection structures and assemblies constructed thereof.
  23. Vinciarelli Patrizio ; Prager Jay, Low profile mounting of power converters with the converter body in an aperture.
  24. Evans Michael D. ; Goss James D. ; Curhan Jeffrey A. ; Vinciarelli Patrizio, Making a connection between a component and a circuit board.
  25. McConnelee Paul A. ; Saia Richard J. ; Durocher Kevin M., Method and fixturing to perform two side laminations of stacked substrates forming 3-D modules.
  26. Saia Richard Joseph (Schenectady NY) Gorowitz Bernard (Clifton Park NY) Durocher Kevin Matthew (Waterford NY), Method for fabricating a stack of two dimensional circuit modules.
  27. Val Christian,FRX, Method for the 3D interconnection of packages of electronic components, and device obtained by this method.
  28. Chua,Swee Kwang; Low,Siu Waf; Chia,Yong Poo; Eng,Meow Koon; Neo,Yong Loo; Boon,Suan Jeung; Huang,Suangwu; Zhou,Wei, Method of making multichip wafer level packages and computing systems incorporating same.
  29. Brooks, Michael, Methods and apparatus for a stacked-die interposer.
  30. Brooks, Michael, Methods and apparatus for a stacked-die interposer.
  31. Vincent, Michael B.; Hayes, Scott M., Microelectronic packages having embedded sidewall substrates and methods for the producing thereof.
  32. Vincent, Michael B.; Hayes, Scott M., Microelectronic packages having embedded sidewall substrates and methods for the producing thereof.
  33. Ameen Joseph George ; Funari Joseph, Multi-layer-multi-chip pyramid and circuit board structure and method of forming same.
  34. Fjelstad, Joseph C.; Haba, Belgacem, Multi-path via interconnection structures and methods for manufacturing the same.
  35. Ference Thomas George, Multiple 3-dimensional semiconductor device processing method and apparatus.
  36. Vinciarelli Patrizio ; Belland Robert E. ; Ead George J. ; Finnemore Fred M. ; Andrus Lance L., Packaging electrical circuits.
  37. Vinciarelli Patrizio ; Belland Robert E. ; Ead George J. ; Finnemore Fred M. ; Andrus Lance L., Packaging electrical circuits.
  38. Vinciarelli Patrizio ; Belland Robert E. ; Ead George J. ; Finnemore Fred M. ; Andrus Lance L., Packaging electrical circuits.
  39. Vinciarelli Patrizio ; Belland Robert E. ; Ead George J. ; Finnemore Fred M. ; Andrus Lance L., Packaging electrical circuits.
  40. Vinciarelli Patrizio (Boston MA) Finnemore Fred (North Reading MA) Balog John S. (Mendon MA) Johnson Brant T. (Concord MA), Packaging electrical components.
  41. Vinciarelli Patrizio ; Finnemore Fred ; Balog John S. ; Johnson Brant T., Packaging electrical components.
  42. Vinciarelli, Patrizio; Finnemore, Fred M.; Lafleur, Michael B.; McCauley, Charles I.; Keay, Gary C.; Nowak, Scott W.; Thompson, Basil, Power converter.
  43. Vinciarelli,Patrizio; Finnemore,Fred M.; McCauley,Charles I.; Keay,Gary C.; Nowak,Scott W.; Thompson,Basil, Power converter body.
  44. Keay Gary C. ; Vinciarelli Patrizio, Power converter connector assembly.
  45. Patrizio Vinciarelli ; Fred M. Finnemore ; Michael B. Lafleur ; Charles I. McCauley, Power converter packaging.
  46. Mermet-Guyennet Michel,FRX, Power electronic device.
  47. Katz Walter M., Routable high-density interfaces for integrated circuit devices.
  48. Katz, Walter M., Routable high-density interfaces for integrated circuit devices.
  49. Tuckerman David B. ; Brathwaite Nicholas E. ; Marella Paul ; Flatow Kirk, Stacked devices for multichip modules.
  50. Gong, Zhiwei; Vincent, Michael B; Hayes, Scott M; Wright, Jason R, Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof.
  51. Gong, Zhiwei; Vincent, Michael B; Hayes, Scott M; Wright, Jason R, Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof.
  52. Gong (Tony), Zhiwei; Vincent, Michael B; Hayes, Scott M; Wright, Jason R, Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof.
  53. Gong, Zhiwei (Tony); Vincent, Michael B; Hayes, Scott M; Wright, Jason R, Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof.
  54. Gong, Zhiwei (Tony); Vincent, Michael B; Hayes, Scott M; Wright, Jason R, Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof.
  55. Yap, Weng F.; Vincent, Michael B., Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof.
  56. Yap, Weng F.; Vincent, Michael B.; Wright, Jason R., Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof.
  57. Fjelstad,Joseph C.; Segaram,Para; Obenhuber,Thomas; Yasumura,Gary, System for making high-speed connections to board-mounted modules.
  58. Lin, Gloria; Gardner, Jr., Bryson; Fisher, Jr., Joseph; Pyper, Dennis; Salehi, Amir, Systems and methods for providing vias through a modular component.
  59. Lin, Gloria; Gardner, Jr., William Bryson; Fisher, Jr., Joseph; Pyper, Dennis; Salehi, Amir, Systems and methods for providing vias through a modular component.
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