$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/82
출원번호 US-0474707 (1990-01-30)
발명자 / 주소
  • Campbell Michael J. (Los Angeles CA) Finn Dennis J. (Los Angeles CA) Tucker George K. (Los Angeles CA) Vahey Michael D. (Manhattan Beach CA) Vedder Rex W. (Playa del Rey CA)
출원인 / 주소
  • Hughes Aircraft Company (Los Angeles CA 02)
인용정보 피인용 횟수 : 229  인용 특허 : 11

초록

A data-flow architecture and software environment for high-performance signal and data procesing. The programming environment allows applications coding in a functional high-level language 20 which a compiler 30 converts to a data-flow graph form 40 which a global allocator 50 then automatically par

대표청구항

A method of data-flow multiprocessing for highly efficient data and signal processing, including the steps of: writing a program of instructions in a high-level language onto a storage medium; reading said program of instructions from said storage medium into a compiler; compiling by said compiler s

이 특허에 인용된 특허 (11)

  1. DeSantis Alfred J. (Berwyn PA) Schibinger Joseph S. (Phoenixville PA), Concurrent processing elements for using dependency free code.
  2. Doyle Donald E. (Delray Beach FL) Hellwarth George A. (Deerfield Beach FL) Quanstrom Jack L. (Boca Raton FL), Data flow component for processor and microprocessor systems.
  3. Misunas David P. (Brighton MA) Dennis Jack B. (Belmont MA), Data processing apparatus for highly parallel execution of stored programs.
  4. Jennings Glenn A. (Riverside CA), Dynamic activity-creating data-driven computer architecture.
  5. Stoughton John W. (Virginia Beach VA) Mielke Roland V. (Virginia Beach VA), Method for concurrent execution of primitive operations by dynamically assigning operations based upon computational mar.
  6. Anastas, Mark S.; Vaughan, Russell F., Modular system controller for a transition machine.
  7. Bolton Brent C. (Austin TX) Hagenmaier ; Jr. Carl F. (Pittstown NJ) Logsdon Gary L. (Round Rock TX) Miner ; Jr. Robert L. (Austin TX), Reduction processor for executing programs stored as treelike graphs employing variable-free applicative language codes.
  8. Masui Shoichi (Kawasaki JPX) Tano Shunichi (Machida JPX) Funabashi Motohisa (Sagamihara JPX) Haruna Koichi (Yokohama JPX), Resource allocation method in a computer system.
  9. Blume ; Jr. Henry M. (Portola Valley CA) Stamm David A. (Santa Clara CA) Budde David L. (San Jose CA), Single chip MOS computer with expandable memory.
  10. Tolle Donald M. (34F Stratford Hills Apts. Chapel Hill NC 27514), Syntactically self-structuring cellular computer.
  11. Barton Robert Stanley (Palo Alto CA) Davis Alan Lynn (Salt Lake City UT) Hauck Erwin Arthur (Arcadia CA) Lyle Don Martin (Huntington Beach CA) Turner Lloyd Drayton (Huntington Beach CA), System and method for concurrent and pipeline processing employing a data driven network.

이 특허를 인용한 특허 (229)

  1. Hawkins, Peter, Acting on a subject system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  11. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  17. Moore, Charles H., Asynchronous computer communication.
  18. Hinker,Paul J., Automatic conversion of source code from 32-bit to 64-bit.
  19. Hunt Galen C., Automatic detection of per-unit location constraints.
  20. Ferry Thomas V. (San Jose CA) Steinweg Russell L. (Santa Clara CA) Zampaglione Michael A. (San Jose CA) Lin Pei H. (San Jose CA), Automatic optimization of a compiled memory structure based on user selected criteria.
  21. Sotheran Martin William,GBX ; Finch Helen R.,GBX, Buffer manager.
  22. Sotheran Martin William,GBX ; Finch Helen R.,GBX, Buffer manager.
  23. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
  24. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
  25. Wise Adrian Philip,GBX ; Sotheran Martin William,GBX, Coding standard token in a system compromising a plurality of pipeline stages.
  26. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  27. Cotter, David, Communications network.
  28. Liem,Clifford, Compiler for multiple processor and distributed memory architectures.
  29. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  30. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  31. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  32. Yoshida Shinichi,JPX ; Muramatsu Tsuyoshi,JPX, Data driven information processor.
  33. Hatakeyama, Kouichi; Takamatsu, Kisho, Data driven information processor carrying out processing using packet stored with plurality of operand data.
  34. Muramatsu Tsuyoshi (Chiba JPX) Yoshida Shinichi (Kashihara JPX) Miyata Souichi (Nara JPX), Data driven type information processor including a combined program memory and memory for queuing operand data.
  35. MacLean, Colin; Cowie, Gordon, Data flow graph.
  36. Adrian Philip Wise GB; Martin William Sotheran GB; William Philip Robbins GB, Data pipeline system and data encoding method.
  37. Wise Adrian Philip,GBX ; Robbins William Philip,GBX ; Sotheran Martin William,GBX, Data pipeline system and data encoding method.
  38. Wise Adrian Philip,GBX ; Robbins William Philip,GBX ; Sotheran Martin William,GBX, Data pipeline system and data encoding method.
  39. Wise Adrian Philip,GBX ; Sotheran Martin William,GBX ; Robbins William Philip,GBX, Data pipeline system and data encoding method.
  40. Wise Adrian Philip,GBX ; Sotheran Martin William,GBX ; Robbins William Philip,GBX, Data pipeline system and data encoding method.
  41. Rhoades, John; Cameron, Ken; Winser, Paul; McConnell, Ray; Faulds, Gordon; McIntosh-Smith, Simon; Spencer, Anthony; Bond, Jeff; Dejaegher, Matthias; Halamish, Danny; Panesar, Gajinder, Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream.
  42. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  43. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  44. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  45. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  46. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  47. Vorbach, Martin, Data processing system.
  48. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
  49. Abali Bulent, Deadlock avoidance method in a computer network.
  50. Hammes,Jeffrey; Poznanovic,Daniel; Gliem,Lonnie, Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation.
  51. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
  52. Anderson, Penelope; Moler, Cleve; Martin, Jos; Shure, Loren, Distributed arrays in parallel computing environments.
  53. Xu,Zhaochang, Distributed-structure-based parallel module structure and parallel processing method.
  54. Hunt, Galen C., Dynamic classification of sections of software.
  55. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.
  56. Seki Hajime,JPX, Electronic computer system and processor element for processing in a data driven manner using reverse polish notation.
  57. Fallah,Farzan; Ghosh,Indradeep, Event-driven observability enhanced coverage analysis.
  58. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  59. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  60. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  61. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  62. Gilbert, Stephen; Beoughter, Ken J.; Lucas, John Michael; Hao, Tennyson; Nixon, Mark J., Graphic element with multiple visualizations in a process environment.
  63. Lucas, John Michael; Nixon, Mark J.; Zhou, Ling; Enver, Alper T.; Webb, Arthur, Graphics integration into a process configuration and control environment.
  64. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
  65. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  66. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  67. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  68. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  69. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  70. Hunt,Galen C., Heavyweight and lightweight instrumentation.
  71. Hunt,Galen C., Heavyweight and lightweight instrumentation.
  72. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.
  73. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  74. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  75. Vorbach,Martin; M��nch,Robert, I/O and memory bus system for DFPS and units with two-or multi-dimensional programmable cell architectures.
  76. Vorbach Martin,DEX ; Munch Robert,DEX, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
  77. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
  78. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
  79. Vorbach,Martin; M?nch,Robert, I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures.
  80. Kimelman,Douglas N.; Rajan,Vadakkedathu T.; Roth,Tova; Wegman,Mark N.; Hogstedt,Karin, Independent net task identification for efficient partition and distribution.
  81. Moore, Charles H., Integrated computer array with independent functional configurations.
  82. Nixon,Mark; Blevins,Terrence L.; Wojsznis,Wilhelm K., Integrated distributed process control system functionality on a single computer.
  83. Blevins,Terrence; Nixon,Mark; Lucas,Michael; Webb,Arthur; Beoughter,Ken, Integration of graphic display elements, process modules and control modules in process plants.
  84. Jones Anthony Mark,GBX, Interface for connecting a bus to a random access memory using a swing buffer and a buffer manager.
  85. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
  86. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
  87. Robbins William Philip,GBX, Inverse modeller.
  88. Fant Karl M., Invocation architecture for generally concurrent process resolution.
  89. Ivanov, Sergei; Haselden, J. Kirk, Linguistic structure for data flow diagrams.
  90. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  91. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  92. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  93. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  94. Rhoades, John, Lookup engine.
  95. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  96. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  97. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  98. Wise, Adrian P.; Dewar, Kevin Douglas; Jones, Anthony Mark; Sotheran, Martin William; Smith, Colin; Finch, Helen Rosemary; Claydon, Anthony Peter J.; Patterson, Donald W. Walker; Barnes, Mark; Kuligo, Memory interface for reading/writing data from/to a memory.
  99. Powell Lawrence J., Method and apparatus for arbitrating resource requests utilizing independent tokens for arbiter cell selection.
  100. Bruell Gregory O. (Carlisle MA), Method and apparatus for defining data packet formats.
  101. Vangal, Sriram R.; Wilson, Howard A., Method and apparatus for driving data packets.
  102. Chalasani Suresh (Los Angeles CA) Varma Anujan M. (Croton-on-Hudson NY), Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconne.
  103. Donaldson,Robert L.; Hudson,Rhett D.; Marshall, Jr.,Lawrence M.; Gray,Michael N.; Sullivan,James J.; Peterson,James B.; Smith,Teresa G.; Klewin,Michael P.; Hawver,Dennis M., Method and apparatus for modeling dataflow systems and realization to hardware.
  104. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  105. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  106. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  107. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  108. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  109. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  110. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  111. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  112. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  113. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  114. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  115. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  116. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
  117. Vorbach, Martin, Method for debugging reconfigurable architectures.
  118. Vorbach, Martin, Method for debugging reconfigurable architectures.
  119. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  120. Vorbach,Martin, Method for debugging reconfigurable architectures.
  121. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
  122. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
  123. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  124. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
  125. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
  126. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  127. May,Frank; N?ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
  128. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
  129. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
  130. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
  131. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
  132. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  133. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  134. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  135. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  136. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
  137. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
  138. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
  139. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
  140. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  141. Ebeling, W. H. Carl; Hogenauer, Eugene B., Method, system and software for programming reconfigurable hardware.
  142. Berkovich Semyon (11918 Stonewood La. Rockville MD 20852) Berkovich Efraim (11918 Stonewood La. Rockville MD 20852), Methods and apparatus for concurrent execution of serial computing instructions using combinatorial architecture for pro.
  143. Lars Olof Mikael Lindberg SE; Ulf Peter Hansson SE; Lars Johan Pettersson SE, Methods and apparatus for dynamically isolating fault conditions in a fault tolerant multi-processing environment.
  144. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  145. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  146. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  147. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
  148. Vorbach, Martin, Methods and devices for treating and/or processing data.
  149. Hammack, Stephen Gerard; Campney, Bruce Hurbert; Zhou, Ling, Methods for a data driven interface based on relationships between process control tags.
  150. Benner Robert E. ; Gustafson John L. ; Montry Gary R., Methods for operating parallel computing systems employing sequenced communications.
  151. Blevins, Terrence L.; Wojsznis, Wilhelm K.; Nixon, Mark J.; Wojsznis, Peter, Multi-objective predictive process optimization with concurrent process simulation.
  152. Wise, Adrian P; Sotheran, Martin W; Robbins, William P; Jones, Anthony M; Finch, Helen R; Boyd, Kevin J; Claydon, Anthony Peter J, Multistandard video decoder and decompression system for processing encoded bit streams including start code detection and methods relating thereto.
  153. Hunt,Galen C., Network independent profiling of applications for automatic partitioning and distribution in a distributed computing environment.
  154. Bar-Or, Amir; Beckerle, Michael James, Optimization model for processing hierarchical data in stream systems.
  155. Wang, Guoqiang; Ravindran, Kaushik; Limaye, Rhishikesh; Yang, Guang; Ghosal, Arkadeb; Andrade, Hugo A.; Allen, John R.; Kornerup, Jacob; Wong, Ian C.; Correll, Jeffrey N.; Trimborn, Michael J., Optimization of a data flow program based on access pattern information.
  156. Funaki Hiroshi (Tokyo JPX), Optimizing compiler which generates multiple instruction streams to be executed in parallel.
  157. Miura Hiroki (Osaka-fu JPX), Parallel computing system with processing element number setting mode and shortest route determination with matrix size.
  158. Tanaka Teruo,JPX ; Hamanaka Naoki,JPX ; Omoda Koichiro,JPX ; Nagashima Shigeo,JPX ; Muramatsu Akira,JPX ; Yoshihara Ikuo,JPX ; Nakao Kazuo,JPX ; Nakagoshi Junji,JPX ; Ojima Kazuo,JPX, Parallel processor system with asynchronous data transmission by a data producing processor to a data using processor em.
  159. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
  160. Shichiku,Ricardo T.; Yoshida,Shinichi, Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium.
  161. Wise Adrian Philip,GBX ; Sotheran Martin William,GBX, Picture end token in a system comprising a plurality of pipeline stages.
  162. Wise Adrian P.,GBX ; Sotheran Martin W,GBX ; Robbins William P.,GBX, Picture start token.
  163. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  164. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  165. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
  166. Bar-Or, Amir; Beckerle, Michael James, Pipeline optimization based on polymorphic schema knowledge.
  167. Wise Adrian Philip,GBX, Pipeline processing machine having a plurality of reconfigurable processing stages interconnected by a two-wire interface bus.
  168. Wise Adrian P.,GBX ; Sotheran Martin W.,GBX ; Robbins William P.,GBX, Pipeline processing machine with interactive stages operable in response to tokens and system and methods relating thereto.
  169. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).
  170. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  171. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).
  172. Blevins, Terrence Lynn; Nixon, Mark J.; McMillan, Gregory K., Process plant monitoring based on multivariate statistical analysis and on-line process simulation.
  173. Blevins, Terrence L.; Beoughter, Ken J.; Lucas, J. Michael; Nixon, Mark J., Process plant user interface system having customized process graphic display layers in an integrated environment.
  174. Todd, Stephen James, Processing of expressions.
  175. Todd, Stephen James, Processing of expressions.
  176. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  177. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  178. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  179. Stark, Gavin J., Processor having a tripwire bus port and executing a tripwire instruction.
  180. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  181. Dennie,Shaun, Protocol for coordinating the distribution of shared memory.
  182. Tsuchie, Koji, Radio communication apparatus and method.
  183. Vorbach, Martin, Reconfigurable elements.
  184. Vorbach, Martin, Reconfigurable elements.
  185. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
  186. Vorbach,Martin; M?nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
  187. Vorbach, Martin, Reconfigurable sequencer structure.
  188. Vorbach, Martin, Reconfigurable sequencer structure.
  189. Vorbach, Martin, Reconfigurable sequencer structure.
  190. Vorbach, Martin, Reconfigurable sequencer structure.
  191. Vorbach,Martin, Reconfigurable sequencer structure.
  192. Vorbach, Martin; Bretz, Daniel, Router.
  193. Vorbach,Martin; Bretz,Daniel, Router.
  194. Vorbach Martin,DEX ; Munch Robert,DEX, Run-time reconfiguration method for programmable units.
  195. Vorbach,Martin; M?nch,Robert, Run-time reconfiguration method for programmable units.
  196. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
  197. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
  198. Rhoades, John; Cameron, Ken; Winser, Paul; McConnell, Ray; Faulds, Gordon; McIntosh-Smith, Simon; Spencer, Anthony; Bond, Jeff; Dejaegher, Matthias; Halamish, Danny; Panesar, Gajinder, SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream.
  199. Hammack, Stephen G.; Campney, Bruce H.; Gilbert, Stephen C.; Sanchez, Adrian A., Scaling composite shapes for a graphical human-machine interface.
  200. Hammack, Stephen G.; Campney, Bruce H.; Gilbert, Stephen C.; Sanchez, Adrian A., Scaling composite shapes for a graphical human-machine interface.
  201. Aoki Shinobu,JPX, Simulation method and simulation system.
  202. Schleiss, Duncan; Ramachandran, Ram; Nixon, Mark; Lucas, Michael, Smart process modules and objects in process plants.
  203. Blevins, Terrence; Nixon, Mark; Lucas, Michael; Webb, Arthur; Beoughter, Ken, Smart process objects used in a process plant modeling system.
  204. Master,Paul L.; Watson,John, Storage and delivery of device features.
  205. Shiraishi Hajime,JPX, Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit usi.
  206. Gentieu,Paul R.; Acquistapace,Tom; Iryami,Farhad, Synchronous network traffic processor.
  207. Ge, Yiqun; Shi, Wuxian; Zhang, Qifan; Huang, Tao; Tong, Wen, System and method for an asynchronous processor with a hierarchical token system.
  208. Bar-Or, Amir; Beckerle, Michael James, System and method for simulating data flow using dataflow computing system.
  209. Gordy, Robert Stephen; Spitzer, Terry, System and method for the distribution of a program among cooperating processing elements.
  210. Gordy, Robert Stephen; Spitzer, Terry, System and method for the distribution of a program among cooperating processing elements.
  211. Fleehart,Timothy G.; Pincus,Jonathan D.; Wallace,Jeffrey S., System and method for whole-system program analysis.
  212. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  213. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  214. Wise Adrian Philip,GBX ; Sotheran Martin William,GBX ; Robbins William P.,GBX, System for microprogrammable state machine in video parser clearing and resetting processing stages responsive to flush token generating by token generator responsive to received data.
  215. Wise Adrian P.,GBX ; Sotheran Martin William,GBX ; Robbins William P.,GBX, System for microprogrammable state machine in video parser disabling portion of processing stages responsive to sequence.
  216. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  217. Wise Adrian P.,GBX ; Dewar Kevin D.,GBX ; Jones Anthony Mark,GBX ; Sotheran Martin William,GBX ; Smith Colin,GBX ; Finch Helen Rosemary,GBX ; Claydon Anthony Peter John,GBX ; Patterson Donald William, Token-based adaptive video processing arrangement.
  218. Hunt, Galen C., Tools and techniques for instrumenting interfaces of units of a software program.
  219. Hunt,Galen C., Tools and techniques for instrumenting interfaces of units of a software program.
  220. Hunt,Galen C., Tools and techniques for instrumenting interfaces of units of a software program.
  221. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
  222. Blevins, Terrence L.; Wojsznis, Wilhelm K.; Nixon, Mark J., Updating and utilizing dynamic process simulation in an operating process environment.
  223. Blevins, Terrence L.; Wojsznis, Wilhelm K.; Nixon, Mark J., Updating and utilizing dynamic process simulation in an operating process environment.
  224. Blevins, Terrence L.; Wojsznis, Wilhelm K.; Nixon, Mark J., Updating and utilizing dynamic process simulation in an operating process environment.
  225. Havekost, Robert B.; Nixon, Mark J., User configurable alarms and alarm trending for process control system.
  226. Wise Adrian P.,GBX ; Birch Nicholas,GBX, Video decompression.
  227. Wise Adrian Philip,GBX, Video decompression and decoding system utilizing control and data tokens.
  228. Wise Adrian P.,GBX ; Boyd Kevin J.,GBX ; Finch Helen R,GBX ; Robbins William P,GBX, Video parser.
  229. Nagda, Jagdish Mooljee; Nielsen, Robert Curt; Peper, Gerri Lynn, Workflow management system for generating output material based on customer input.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트