초록 ▼

A multi-layered structure of wirings on a semiconductor substrate has been employed in conjuction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step o

A multi-layered structure of wirings on a semiconductor substrate has been employed in conjuction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.

대표청구항 ▼

A semiconductor integrated circuit device comprising: a semiconductor substrate having a plurality of semiconductor devices formed on a main plane; a first insulator film being formed over said main plane of said semiconductor substrate; first wirings being formed on said first insulator film and ea

A semiconductor integrated circuit device comprising: a semiconductor substrate having a plurality of semiconductor devices formed on a main plane; a first insulator film being formed over said main plane of said semiconductor substrate; first wirings being formed on said first insulator film and each of said first wirings extending in a first direction; a second insulator film being formed on said first wirings; second wirings being formed on said second insulator film; a third insulator film being formed on said second wirings, wherein said third insulator film is formed with holes so as to expose surface portions respectively associated with said second wirings, and wherein each of said holes is respectively disposed over a corresponding pair of adjacent first wirings; a plurality of bump electrodes being electrically connected to said second wirings via said holes, respectively; a plurality of dummy wiring patterns being formed between each said pair of adjacent first wirings at a location thereof only in and around said holes corresponding to a transverse area in accordance with an orthogonal projection of said holes toward said semiconductor substrate, wherein said plurality of dummy wiring patterns are arranged in said first direction with a predetermined distance therebetween.