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Process for preventing a native oxide from forming on the surface of a semiconductor material and integrated circuit cap 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-000/00
출원번호 US-0605748 (1990-10-30)
발명자 / 주소
  • Doan Trung T. (Boise ID) Lowrey Tyler A. (Boise ID)
출원인 / 주소
  • Micron Technology, Inc. (Boise ID 02)
인용정보 피인용 횟수 : 77  인용 특허 : 5

초록

A process for forming silicon nitride layers on silicon substrates which includes initially heating the silicon substrates in a rapid thermal processor and in a substantially oxygen-free and residual moisture free environment to form a thin Si3N4 layer directly on the silicon surface which is free o

대표청구항

A process for forming a silicon nitride, Si3N4, dielectric layer on the surface of a silicon substrate while substantially eliminating the formation of a native silicon oxide or silicon dioxide on the silicon substrate surface, which includes the steps of: a. cleaning said surface of said silicon su

이 특허에 인용된 특허 (5)

  1. Brown William D. (Fayetteville AR) Khaliq Muhammad A. (Mankato MN), Annealing process to stabilize PECVD silicon nitride for application as the gate dielectric in MOS devices.
  2. Nozaki Takao (Yokohama JPX) Ito Takashi (Kawasaki JPX) Arakawa Hideki (Yokohama JPX) Ishikawa Hajime (Yokohama JPX) Shinoda Masaichi (Sagamihara JPX), Method for forming a nitride insulating film on a silicon semiconductor substrate surface by direct nitridation.
  3. Freeman Dean W. (Garland TX) Burris James B. (Dallas TX) Davis Cecil J. (Greenville TX) Loewenstein Lee M. (Plano TX), Method for wafer treating.
  4. Allman Derryl D. J. (Colorado Springs CO) Lee Steven S. (Colorado Springs CO), Native oxide reduction for sealing nitride deposition.
  5. Beguwala Moiz M. E. (Placentia CA) Erdmann Francis M. (Anaheim CA), Process for direct thermal nitridation of silicon semiconductor devices.

이 특허를 인용한 특허 (77)

  1. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  2. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  3. Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer.
  4. DeBoer, Scott J.; Powell, Don C., Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer.
  5. DeBoer,Scott J.; Powell,Don C., Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer.
  6. Moore, John T.; DeBoer, Scott J., Capacitors.
  7. Moore,John T.; DeBoer,Scott J., Capacitors, methods of forming capacitors, and methods of forming capacitor dielectric layers.
  8. Iyer Ravi ; Tran Luan ; Turner Charles L., Depletion compensated polysilicon electrodes.
  9. Iyer Ravi ; Tran Luan ; Turner Charles L., Depletion compensated polysilicon electrodes.
  10. Iyer Ravi ; Tran Luan ; Turner Charles L., Depletion compensated polysilicon electrodes.
  11. Iyer, Ravi; Tran, Luan; Turner, Charles L., Depletion compensated polysilicon electrodes.
  12. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  13. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  14. Roberson ; Jr. Glenn A. (Hollister CA) Genco Robert M. (Atlanta GA) Mundt G. Kyle (Duluth GA), Docking and environmental purging system for integrated circuit wafer transport assemblies.
  15. Roberson ; Jr. Glenn A. ; Genco Robert M. ; Mundt G. Kyle, Docking and environmental purging system for integrated circuit wafer transport assemblies.
  16. Roberson ; Jr. Glenn A. ; Genco Robert M. ; Mundt G. Kyle, Docking and environmental purging system for integrated circuit wafer transport assemblies.
  17. Clementi Cesare (Busto Arsizio ITX) Ghidini Gabriella (Milan ITX) Tosi Marina (Trezzo sull\Adda ITX), EPROM cell with a readily scalable interpoly dielectric.
  18. Ahn,Kie Y.; Forbes,Leonard, Electronic apparatus with deposited dielectric layers.
  19. Ahn, Kie Y.; Forbes, Leonard, HfAlOfilms for gate dielectrics.
  20. Ma Yi ; Merchant Sailesh Mansinh ; Roy Pradip Kumar, Layered silicon nitride deposition process.
  21. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
  22. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
  23. Thakur Randhir P. S. ; Sandhu Gurtej Singh, Method for fabricating stacked layer silicon nitride for low leakage and high capacitance.
  24. Hey H. Peter W ; Carlson David, Method for in-situ cleaning of native oxide from silicon surfaces.
  25. Cheng-Che Lee TW; Chung-Chih Liu TW, Method for preventing native oxide growth during nitridation.
  26. Ahn,Kie Y.; Forbes,Leonard, Method including forming gate dielectrics having multiple lanthanide oxide layers.
  27. Moore, John T.; DeBoer, Scott J., Method of forming a capacitor dielectric layer.
  28. DeBoer, Scott J.; Powell, Don C., Method of forming a capacitor electrode having an interface layer of different chemical composition from a bulk layer.
  29. Sandhu, Gurtej S.; Moore, John T.; Rueger, Neal R., Method of forming a nitrogen-enriched region within silicon-oxide-containing masses.
  30. Chen, Gary, Method of forming a semiconductor contact that includes selectively removing a Ti-containing layer from the surface.
  31. Beaman, Kevin L.; Moore, John T., Method of forming a structure over a semiconductor substrate.
  32. Beaman, Kevin L.; Moore, John T., Method of forming a structure over a semiconductor substrate.
  33. Beaman,Kevin L.; Moore,John T., Method of forming a structure over a semiconductor substrate.
  34. DeBoer, Scott Jeffrey; Schuegraf, Klaus Florian; Thakur, Randhir P. S.; Carstensen, Robert K., Method of forming silicon nitride layer directly on HSG polysilicon.
  35. Moore, John T., Method of forming transistors associated with semiconductor substrates comprising forming a nitrogen-comprising region across an oxide region of a transistor gate.
  36. Choi Jeong Yeol, Method of improving the reliability of low-voltage programmable antifuse.
  37. Neukermans Armand P. (Palo Alto CA), Method of making superhard mechanical microstructures.
  38. Itoh, Kae; Hamakubo, Katsushi; Shimokawa, Koichi, Method of producing a magnetic recording disc.
  39. Ahn, Kie Y.; Forbes, Leonard, Methods for atomic-layer deposition.
  40. Ahn,Kie Y.; Forbes,Leonard, Methods for atomic-layer deposition of aluminum oxides in integrated circuits.
  41. Sandhu,Gurtej S.; Moore,John T.; Rueger,Neal R., Methods of forming a nitrogen enriched region.
  42. Moore, John T.; DeBoer, Scott J., Methods of forming capacitors.
  43. Eppich,Denise M.; Beaman,Kevin L., Methods of forming capacitors and methods of forming capacitor dielectric layers.
  44. Moore, John T., Methods of forming dielectric materials and methods of processing semiconductor substrates.
  45. Moore, John T., Methods of forming oxide regions over semiconductor substrates.
  46. Moore, John T., Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices.
  47. Beaman, Kevin L.; Moore, John T., Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates.
  48. Beaman,Kevin L.; Moore,John T., Methods of forming transistors.
  49. Sandhu,Gurtej S.; Moore,John T.; Rueger,Neal R., Methods of forming transistors.
  50. Moore, John T., Methods of forming transistors associated with semiconductor substrates.
  51. Sandhu, Gurtej S.; Moore, John T.; Rueger, Neal R., Methods of incorporating nitrogen into silicon-oxide-containing layers.
  52. Ahn, Kie Y., Methods, systems, and apparatus for uniform chemical-vapor depositions.
  53. Ahn,Kie Y., Methods, systems, and apparatus for uniform chemical-vapor depositions.
  54. Glenn A. Roberson, Jr. ; Robert M. Genco ; Robert B. Eglinton ; Wayland Comer ; Gregory K. Mundt, Molecular contamination control system.
  55. Roberson ; Jr. Glenn A. ; Genco Robert M. ; Eglinton Robert B. ; Comer Wayland ; Mundt Gregory K., Molecular contamination control system.
  56. Roberson ; Jr. Glenn A. ; Genco Robert M. ; Eglinton Robert B. ; Comer Wayland ; Mundt Gregory K., Molecular contamination control system.
  57. Roberson ; Jr. Glenn A. ; Genco Robert M. ; Eglinton Robert B. ; Comer Wayland ; Mundt Gregory K., Molecular contamination control system.
  58. Yamauchi, Toshiharu; Yamauchi, Tunenori; Toyota, Kumiko, Nitride film forming method, semiconductor device fabrication method, capacitor fabrication method and nitride film forming apparatus.
  59. Arkadii V. Samoilov ; Dale R. DuBois ; Bradley M. Curelop ; David R. Carlson ; Paul B. Comita, Process and apparatus for cleaning a silicon surface.
  60. Chao Tien S. (Hsinchu TWX) Chu Chih-Hsun (Hsinchu TWX), Process for suppressing boron penetration in BF2+-implanted P+-poly-Si gate us.
  61. Beaman, Kevin L.; Moore, John T., Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates.
  62. Moore,John T., Semiconductor constructions.
  63. Kasai Yoshio,JPX ; Suzuki Takashi,JPX ; Tsuda Takanori,JPX ; Mikata Yuuichi,JPX ; Akahori Hiroshi,JPX ; Yamamoto Akihito,JPX, Semiconductor device applied to composite insulative film and manufacturing method thereof.
  64. Kasai Yoshio,JPX ; Suzuki Takashi,JPX ; Tsuda Takanori,JPX ; Mikata Yuuichi,JPX ; Akahori Hiroshi,JPX ; Yamamoto Akihito,JPX, Semiconductor device applied to composite insulative film manufacturing method thereof.
  65. Doan Trung Tri, Semiconductor processing method of depositing polysilicon.
  66. Doan Trung Tri, Semiconductor processing method of reducing thickness depletion of a silicide layer at a junction of different underlying layers.
  67. Chen, Gary, Semiconductor substrate cleaning.
  68. Chen,Gary, Semiconductor substrate cleaning.
  69. Yang, Wan-Cheng; Lee, Ren-Dou, Silicon nitride furnace tube low temperature cycle purge for attenuated particle formation.
  70. Reisinger, Hans; Lehmann, Volker; Stengl, Reinhard; Wendt, Hermann; Lange, Gerrit; Bachhofer, Harald; Franosch, Martin; Schafer, Herbert, Storage capacitor for a DRAM.
  71. Agarwal, Vishnu K., Structures and methods for improved capacitor cells in integrated circuits.
  72. Agarwal,Vishnu K., Structures and methods for improved capacitor cells in integrated circuits.
  73. Ahn, Kie Y.; Forbes, Leonard, Systems with a gate dielectric having multiple lanthanide oxide layers.
  74. Moore, John T., Transistor devices.
  75. Sandhu,Gurtej S.; Moore,John T.; Rueger,Neal R., Transistor structures.
  76. Sandhu, Gurtej S.; Moore, John T.; Rueger, Neal R., Transistor structures, methods of incorporating nitrogen into silicon-oxide-containing layers; and methods of forming transistors.
  77. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.

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