$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Intergrated circuit element having a planar, solvent-free dielectric layer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/28
출원번호 US-0387852 (1989-07-31)
발명자 / 주소
  • Fischer, Paul J.
출원인 / 주소
  • W. L. Gore & Associates, Inc.
대리인 / 주소
    Mortenson & Uebler
인용정보 피인용 횟수 : 37  인용 특허 : 8

초록

An integrated circuit element is provided, which may be an active or passive element, comprising a planar dielectric layer having a thickness 25 micrometers or less and a dielectric constant less than 3.4. The dielectric layer is preferably a fluoropolymer film coated or impregnated with a low ionic

대표청구항

1. An integrated circuit element comprising a base wafer having an integrated circuit thereon, said circuit being covered by a dry planar, substantially solvent-free dielectric layer, wherein said dielectric layer comprises a porous plastic matrix layer containing within at least some of its pores a

이 특허에 인용된 특허 (8)

  1. Johnson Daniel D. (Yorklyn DE), Dielectric materials.
  2. Hatakeyama Minoru (Sakuragaokanishi JPX) Moriya Kosuke (Okayama JPX) Komada Ichiro (Okayama JPX), Flexible printed circuit board base material.
  3. Ashwell Gareth W. B. (Ipswich GB2), Heterogeneous conformal CVD of arsenosilicate glass.
  4. Carson Dennis W. (Lower Burrell PA) Schmitt Robert J. (Pittsburgh PA) Seneker Carl A. (Pittsburgh PA) Van Kuren Thomas A. (Dublin OH) Wallace David R. (Dublin OH), Method of providing a substrate with a flexible multilayer coating.
  5. Hartman Frederick N. (Wilmington DE) Knight Alan C. (Parkersburg WV), Multilayer circuit board with fluoropolymer interlayers.
  6. Suzuki Hirosuke (Tokorozawa JPX), Multilayer printed circuit board.
  7. Komada Ichiro (Okayama JPX) Hatakeyama Minoru (Sakuragaokanishi JPX), Printed circuit board base material.
  8. Mase Yasukazu (Tokyo JPX) Abe Masahiro (Yokohama JPX) Aoyama Masaharu (Fujisawa JPX) Ajima Takashi (Kamakura JPX), Semiconductor device of multilayer wiring structure.

이 특허를 인용한 특허 (37)

  1. Korleski ; Jr. Joseph E., Adhesive-filler film composite.
  2. Davis Charles R. (Wappingers Falls NY) Egitto Frank D. (Binghamton NY) Skarvinko Eugene R. (Binghamton NY), Design of high density structures with laser etch stop.
  3. Ogawa, Makoto; Urakami, Akira; Ohashi, Kazuhiko, Dielectric film for printed wiring board, multilayer printed board, and semiconductor device.
  4. Paul J. Fischer ; Robin E. Gorrell ; Mark F. Sylvester, Dimensionally stable core for use in high density chip packages and a method of fabricating same.
  5. Richards John Gareth ; Flores Hector ; Sander Wendell B., Electrical apparatus with a metallic layer coupled to a lower region of a substrate and a metallic layer coupled to a lo.
  6. Fischer Paul J. ; Korleski Joseph, Electronic chip package.
  7. Fischer, Paul J.; Korleski, Joseph E., Electronic chip package.
  8. Richards John G. (San Jose CA) Flores Hector (San Jose CA) Sander Wendell B. (Los Gatos CA), Fabricating a semiconductor with an insulative coating.
  9. Budnaitis John J., High planarity and low thermal coefficient of expansion base for semi-conductor reliability screening.
  10. Brooks J. Mike ; King Jerrold L. ; Schofield Kevin, Integrated circuit device having cyanate ester buffer coat.
  11. Brooks, J. Mike; King, Jerrold L.; Schofield, Kevin, Integrated circuit device having cyanate ester buffer coat and method of fabricating same.
  12. Sterrett, Terry; Chen, Tim, Integrated circuit device with covalently bonded connection structure.
  13. Wojnarowski Robert J. (Ballston Lake NY) Cole Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Scotia NY) Daum Wolfgang (Schenectady NY), Low Dielectric constant materials for high speed electronics.
  14. Rosenmayer C. Thomas, Low dielectric constant material for use as an insulation element in an electronic device.
  15. Rosenmayer C. Thomas, Low dielectric constant material for use as an insulation element in an electronic device.
  16. Rosenmayer C. Thomas, Low dielectric constant material with improved dielectric strength.
  17. Miller, Alan G., Machine for the production of formed patties with a hand made appearance, and method for interleaving paper and stacking.
  18. Greenawalt, Keith E., Making a soft tissue prosthesis for repairing a defect of an abdominal wall or a pelvic cavity wall.
  19. King David R. (Elkton MD) Adler Gary C. (Newark DE) Korleski Joseph E. (Newark DE) Waters Michelle M. H. (Hockessin DE), Matched low dielectric constant, dimensionally stable adhesive sheet.
  20. Sterrett,Terry; Chen,Tim, Method and apparatus for improving an integrated circuit device.
  21. Brooks J. Mike ; King Jerrold L. ; Schofield Kevin, Method of forming an integrated circuit device having cyanate ester buffer coat.
  22. J. Mike Brooks ; Jerrold L. King ; Kevin Schofield, Method of forming an integrated circuit device having cyanate ester buffer coat.
  23. Budnaitis John J., Method of making a high planarity, low CTE base for semiconductor reliability screening.
  24. Hughes Henry G. (Scottsdale AZ) Lue Ping-Chang (Scottsdale AZ) Robinson Frederick J. (Scottsdale AZ), Method of making a semiconductor device having a low permittivity dielectric.
  25. Matsuda Tetsuo (Poughkeepsie NY) Okumura Katsuya (Poughkeepsie NY), Method of planarizing a semiconductor workpiece surface.
  26. Budnaitis John J. ; Leong Jimmy, Method of wafer level burn-in.
  27. Hiraoka, Toshiro; Hotta, Yasuyuki; Asakawa, Koji; Matake, Shigeru, Passive element component and substrate with built-in passive element.
  28. Suzuki,Takeshi; Tomekawa,Satoru; Kawakita,Yoshihiro; Nakagiri,Yasushi; Echigo,Fumio, Process for manufacturing a circuit board.
  29. Wojnarowski Robert J. (Ballston Lake NY) Cole Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Scotia NY) Daum Wolfgang (Schenectady NY), Processing low dielectric constant materials for high speed electronics.
  30. Wojnarowski Robert John ; Cole Herbert Stanley ; Sitnik-Nieters Theresa Ann ; Daum Wolfgang, Processing low dielectric constant materials for high speed electronics.
  31. Cheung Robin W. ; Chang Mark S., Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance.
  32. Suzuki, Takeshi; Tomekawa, Satoru; Kawakita, Yoshihiro; Nakagiri, Yasushi; Echigo, Fumio, Resin board, manufacturing process for resin board, connection medium body, circuit board and manufacturing process for circuit board.
  33. Suzuki, Takeshi; Tomekawa, Satoru; Kawakita, Yoshihiro; Nakagiri, Yasushi; Echigo, Fumio, Resin board, manufacturing process for resin board, connection medium body, circuit board and manufacturing process for circuit board.
  34. Richards John G. ; Flores Hector, Resistor fabrication.
  35. Greenawalt, Keith E., Soft tissue prosthesis for repairing a defect of an abdominal wall or a pelvic cavity wall.
  36. Budnaitis John J., Wafer level burn-in base unit substrate and assembly.
  37. Budnaitis John J. ; Leong Jimmy, Wafer level burn-in system.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트