[특허]Integrated circuit processing system

Integrated circuit processing system 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	B65G-049/05
출원번호	US-0143918 (1988-01-13)
발명자 / 주소	Davis Cecil J. (Greenville TX) Matthews Robert (Plano TX) Bowling Robert A. (Garland TX)
출원인 / 주소	Texas Instruments Incorporated (Dallas TX 02)
인용정보	피인용 횟수 : 78 인용 특허 : 0

초록 ▼

A vacuum-tight wafer carrier, and a load lock suitable for use with this wafer carrier. The wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shelf. This reduces generation of particulates by abrasion of the surface of the wafer. The carrier also contains elastic elements to restrain the wafers from rattling around, which further reduces the internal generation of particulates. When the wafer carrier is placed into the load lock, its body is lowered from beneath its cover through an aperture into a lower chamber, where wafers are loaded and unloaded under vacuum; the carrier cover remains covering the aperture into the lower chamber, so that the wafers never see any surface which is directly exposed to atmosphere. A wafer transport arm mechanism permits interchange of wafers among one or more processing stations and one or more load locks of this type.

대표청구항 ▼

A method for fabricating integrated circuits, comprising the steps of: providing a plurality of wafers in a vacuum sealable wafer carrier, said wafer carrier comprising a bell jar shape cover which is vacuum sealable to a body thereof, said bell jar shape cover being removable from said body in a direction which is substantially normal to the plane of wafers supported in said body; placing said wafer carrier into a vacuum sealable load lock upper chamber having a partial floor with an aperture therein and a stage positioned below said aperture in close proximity to said floor; pumping down said load lock upper chamber to a pressure less than 10 to the -4 Torr; lowering said stage in a linear, vertical direction, so that said bell jar shape cover remains supported on said partial floor in said upper process chamber while said body including wafers is lowered into the lower chamber; transferring wafers in a desired sequence from said wafer carrier under vacuum to one or more selected process stations which are enclosed inside a connecting contiguous vacuum-tight space with said lower chamber until a desired sequence of processing operations has been completed; and then raising said stage to rejoin said wafer carrier body with said wafer carrier bell jar shape cover and again effect a vacuum seal therebetween; venting said upper chamber to ambient; and removing said wafer carrier from said upper chamber.

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Kurita, Shinichi; Blonigan, Wendell T.; Tanase, Yoshiaki, Large area substrate transferring method for aligning with horizontal actuation of lever arm.
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Kurita,Shinichi; Blonigan,Wendell T.; Tanase,Yoshiaki, Load lock chamber for large area substrate processing system.
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Kurita,Shinichi; Blonigan,Wendell T., Load lock chamber having two dual slot regions.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Integrated circuit processing system 원문보기

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Integrated circuit processing system 원문보기

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