[특허]Semiconductor integrated circuit device and method of manufacturing the same

Semiconductor integrated circuit device and method of manufacturing the same 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-027/10
출원번호	US-0422640 (1989-10-17)
우선권정보	JP-0261035 (1988-10-17)
발명자 / 주소	Owada Nobuo (Ohme JPX) Akimori Hiroyuki (Ohme JPX) Nitta Takahisa (Fuchuu JPX) Kobayashi Tohru (Iruma JPX) Sasabe Shunji (Iruma JPX) Kawaji Mikinori (Hino JPX) Kasahara Osamu (Hinode JPX)
출원인 / 주소	Hitachi, Ltd. (Tokyo JPX 03)
인용정보	피인용 횟수 : 35 인용 특허 : 0

초록 ▼

Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction. The wiring pitches of the second-layer wiring lines and the third-layer wiring lines are set substantially equal to or smaller than the wiring pitch of th first-layer wiring lines. As a further aspect of the present invention, the ratio of wiring pitch of third-layer wiring lines to first-layer wiring lines can be 0.5, 1.0, 1.5 or 2.0. In addition, insulator films on which are formed the wiring lines are respectively subjected to flattening processes in order to flatten their upper surfaces, prior to providing the wiring lines thereon.

대표청구항 ▼

A semiconductor integrated circuit device adopting a gate array scheme wherein circuits constructed of basic cells, which are arranged in a matrix array, are electrically connected by a plurality of layers of wiring, comprising: a semiconductor substrate having (1) basic cell forming regions, in which said basic cells are arranged in the matrix array, and (2) wiring channel regions, said wiring channel regions respectively being located between adjacent basic cell forming regions; first-layer wiring lines which are arranged at a position overlying said wiring channel regions; a first-layer inter-layer insulator film which is formed so as to cover said basic cells in said basic cell forming regions and said first-layer wiring lines overlying said wiring channel regions; second-layer wiring lines which are arranged at a position overlying said basic cell forming regions and overlying said wiring channel regions, and lying on said first-layer inter-layer insulator film, and which extend in a second direction different from a first extending direction, of said first-layer wiring lines, said wiring channel regions also extending in said first extending direction; a second-layer inter-layer insulating film which is formed so as to cover said first-layer inter-layer insulator film and said second-layer wiring lines; and third-layer wiring lines which are arranged at a position overlying said basic cell forming regions and overlying said wiring channel regions, and lying on said second-layer inter-layer insulator film, and which extend in a third direction, a wiring pitch of said third-layer wiring lines being substantially equal to or smaller than that of said first-layer wiring lines.

이 특허를 인용한 특허 (35)

Sakai, Isami, Composite semiconductor integrated circuit device.
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Bui Nguyen Duc (San Jose CA) Wollesen Donald L. (Saratoga CA), Enhanced electromigration lifetime of metal interconnection lines.
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Nakagawa, Kenji, IC bonding pad combined with mark or monitor.
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Pasch Nicholas F. (Pacifica CA) Butkus Aldona M. (Santa Clara CA), Integrated circuit structure having reduced cross-talk and method of making same.
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Shinagawa Noriaki,JPX, Integrated circuit with gate-array interconnections routed over memory area.
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Stolmeijer Andre, Interconnect scheme for integrated circuits.
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Kim,Hyun Young; Yoon,Joo Sun; Kim,Bong Ju; Tae,Seung Gyu, Lower substrate, display apparatus having the same and method of manufacturing the same.
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Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.
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Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.
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Tobben Dirk ; Weber Stefan J. ; Brintzinger Axel, Method for forming a semiconductor fuse.
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Efland Taylor R. ; Cotton David ; Skelton Dale J., Method of making a multiple transistor integrated circuit with thick copper interconnect.
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Ogawa,Tsuyoshi; Nishitani,Yuji, Multi-chip circuit module and method for producing the same.
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Efland Taylor R. ; Cotton David ; Skelton Dale J., Multiple transistor integrated circuit with thick copper interconnect.
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Cleeves, James M.; Scheuerlein, Roy E., Optimization of critical dimensions and pitch of patterned features in and above a substrate.
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Cleeves, James M.; Scheuerlein, Roy E., Optimization of critical dimensions and pitch of patterned features in and above a substrate.
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Cleeves,James M.; Scheuerlein,Roy E., Optimization of critical dimensions and pitch of patterned features in and above a substrate.
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Bui Nguyen Duc ; Wollesen Donald L., Reduced electromigration interconnection line.
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Kuge Shigehiro,JPX ; Arimoto Kazutami,JPX ; Tsukude Masaki,JPX ; Fujishima Kazuyasu,JPX, Semiconductor device comprising a plurality of interconnection patterns.
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Shigehiro Kuge JP; Kazutami Arimoto JP; Masaki Tsukude JP; Kazuyasu Fujishima JP, Semiconductor integrated circuit.
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Yoshida Yuji,JPX, Semiconductor integrated circuit chip.
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Okumura Koichiro (Tokyo JPX), Semiconductor integrated circuits with specific pitch multilevel interconnections.
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Kawata Masato,JPX, Semiconductor memory device having a plurality of wiring layers.
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Noguchi, Mitsuhiro; Nishiyama, Akira, Semiconductor with multilayer metal structure using copper that offer high speed performance.
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Mitsuhiro Noguchi JP; Akira Nishiyama JP, Semiconductor with multilayer wiring structure that offer high speed performance.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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Lin,Mou Shiung, Top layers of metal for high performance IC's.
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Lin,Mou Shiung, Top layers of metal for high performance IC's.
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Lin,Mou Shiung, Top layers of metal for high performance IC's.
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Lin,Mou Shiung, Top layers of metal for high performance IC's.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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Semiconductor integrated circuit device and method of manufacturing the same 원문보기

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Semiconductor integrated circuit device and method of manufacturing the same 원문보기

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