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Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/48
출원번호 US-0287582 (1988-12-16)
발명자 / 주소
  • Broadbent Eliot K. (San Jose CA)
출원인 / 주소
  • North American Philips Corp., Signetics Division (Sunnyvale CA 02)
인용정보 피인용 횟수 : 37  인용 특허 : 0

초록

A planar electrical interconnection system suitable for an integrated circuit is created by a process in which an insulating layer (31) having a planar upper surface is formed on a substructure after which openings (32) are etched through the insulating layer. A conductive planarizing layer (33) hav

대표청구항

A method wherein a first electrically insulating layer having a largely planar upper surface is formed on a substructure, and first openings are etched through the first insulating layer down to the substructure, characterized by the steps of: forming a first electrically conductive planarizing laye

이 특허를 인용한 특허 (37)

  1. Yanaki, Jamal S., Active electrode for transdermal medicament administration.
  2. Yanaki, Jamal S., Active transdermal medicament patch and circuit board for same.
  3. Joshi, Ashok V., Apparatus and methods for fluid delivery using electroactive needles and implantable electrochemical delivery devices.
  4. Teig, Steven; Fujimura, Akira; Caldwell, Andrew, Circular vias and interconnect-line ends.
  5. Gris, Yvon, Conductive line formed on integrated circuits.
  6. Rolfson J. Brett, Integrated circuit and method for forming and integrated circuit.
  7. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit having conductors of enhanced cross-sectional area.
  8. Rolfson J. Brett, Integrated circuit, and method for forming an integrated circuit.
  9. Motsiff William Thomas ; Geffken Robert Michael ; Uttecht Ronald Robert, Integrated pad and fuse structure for planar copper metallurgy.
  10. Stolmeijer Andre, Interconnect scheme for integrated circuits.
  11. Rolfson J. Brett, Interlocking conductive plug for use with an integrated circuit.
  12. Joshi,Ashok V., Iontophoretic drug delivery systems.
  13. Joshi,Ashok V., Iontophoretic fluid delivery device.
  14. Joshi, Ashok V., Iontophoretic treatment device.
  15. Kim Sang Young (Seoul KRX) Song Yung Wook (Seoul KRX) Kim Hun Do (Seoul KRX), Method for filling contact holes with metal by two-step deposition.
  16. Kim,Deok Yong, Method for manufacturing a semiconductor wafer.
  17. Gris Yvon,FRX, Method of formation of conductive lines on integrated circuits.
  18. Charles H. Dennison ; Raymond A. Turi, Method of forming dual conductive plugs.
  19. Dennison Charles H. ; Turi Raymond A., Method of forming dual conductive plugs.
  20. Matsuura Masazumi,JPX, Method of making a semiconductor device.
  21. Cohn, Charles; Hawk, Jr., Donald Earl, Method of manufacturing an integrated circuit package.
  22. Tze-Liang Lee TW; Mong-Song Liang TW, Method of protecting a copper pad structure during a fuse opening procedure.
  23. Miller Dennis Brian ; O'Malley Grace M. ; Kemper Brian R., Microelectronic assembly with connection to a buried electrical element, and method for forming same.
  24. Miller Dennis Brian ; O'Malley Grace M. ; Kemper Brian R., Microelectronic assembly with connection to a buried electrical element, and method for forming same.
  25. Massingill, Thomas J.; McCormack, Mark Thomas; Wang, Wen-Chou Vincent, Multi-chip module and method for forming and method for deplating defective capacitors.
  26. Hunt Hang Jiang ; Yasuhito Takahashi ; Michael Guang-Tzong Lee ; Wen-chou Vincent Wang ; Mark McCormack, Multilayer circuit structure build up method.
  27. Doan Trung T. ; Dennison Charles H., Planarization of a gate electrode for improved gate patterning over non-planar active area isolation.
  28. Tobin Jeffrey A. ; Benzing Jeffrey C. ; Broadbent Eliot K. ; Rough J. Kirkwood H., Plasma process apparatus for integrated circuit fabrication having dome-shaped induction coil.
  29. Yu,Wen; Besser,Paul Raymond, Semiconductor component and method of manufacture.
  30. Matsunaga,Noriaki, Semiconductor device and a method of manufacturing the semiconductor device.
  31. Kasai Naoki,JPX, Semiconductor device capable of easily filling contact conductor plug in contact hole.
  32. Takata, Yoshifumi; Sakai, Yuichi; Chibahara, Hiroyuki; Iwasaki, Masanobu, Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof.
  33. Nakabayashi, Masakazu, Semiconductor device having complementary MOS transistor.
  34. Zhang, Lei; Jiang, Hunt Hang, Structure and method for forming a multilayered structure.
  35. Lin Chi-Fa,TWX, Suppression of interconnect stress migration by refractory metal plug.
  36. Yu,Chris C.; Doan,Trung T., Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs.
  37. Sardella John C., Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in which they are formed.
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