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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0323779 (1989-03-15) |
| 발명자 / 주소 |
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| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 548 인용 특허 : 0 |
An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting from tolerances which must be allowed for regi
An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting from tolerances which must be allowed for registration of masks used in successive steps in forming the semiconductor structures, spacers are formed with reference to the position of existing elements in order to form floating gates and define small areas of these gates where, in a controlled fashion, a tunnel erase dielectric is formed. Alternatively, a polysilicon strip conductor is separated into separate control gates by a series of etching steps that includes an anisotropic etch of boundary oxide layers to define the area of the control gates that are coupled to the erase gate through an erase dielectric. In either case, the polysilicon layer strip can alternatively be separated by growing oxide thereon until it is completely consumed. A technique for forming a pure oxide dielectric layer of uniform thickness includes depositing a thin layer of an undoped polysilicon material and then oxidizing its surface until substantially the entire undoped polysilicon layer is consumed and made part of the resulting oxide layer. Overlapping doped regions are provided in the substrate by an ion implantation mask that adds spacers to the mask aperture to change its size between implants.
A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of: forming a first plurality of continuous elongated parallel strips of conductive material on said substrate in a manner to be insul
A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of: forming a first plurality of continuous elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer, forming a second plurality of continuous elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other, thereafter forming spacers along opposing edges of adjacent ones of said second plurality of parallel strips and extending toward each other but leaving a defined space therebetween, and thereafter forming a gap in said first plurality of strips through the space defined by the spacers, thereby forming electrically isolated floating gates from said first plurality of strips.
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