$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Full wafer integrated circuit testing device

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/02
출원번호 US-0532481 (1990-06-04)
발명자 / 주소
  • Kwon Oh-Kyong (Plano TX) Hashimoto Masashi (Garland TX) Malhi Satwinder (Garland TX) Born Eng C. (Richardson TX)
출원인 / 주소
  • Texas Instruments Incorporated (Dallas TX 02)
인용정보 피인용 횟수 : 288  인용 특허 : 0

초록

A full wafer integrated circuit testing device (10) tests integrated circuits (15) formed as a wafer in conjunction with a test control unit (40). Probe units (14) associate with respective integrated circuits (15). Probe tips (16) on probe units (14) communicate with respective pads (19) with the i

대표청구항

An integrated circuit testing device simultaneously connected to a plurality of subject integrated circuits for testing substantially all of said plurality of subject integrated circuits formed on a semiconductor wafer, said testing device connected to and operating in conjunction with a test contro

이 특허를 인용한 특허 (288)

  1. Wang, Mill-Jer; Chen, Chih-Chia; Lin, Hung-Chih; Peng, Ching-Nen; Chen, Hao, 3D IC testing apparatus.
  2. Wang, Mill-Jer; Chen, Chih-Chia; Lin, Hung-Chih; Peng, Ching-Nen; Chen, Hao, 3D IC testing apparatus.
  3. Lai, Hung-Wei; Lee, Tsung-Jun, Active probe card.
  4. Kline Eric, Active wafer level contacting system.
  5. Kuo,Yian Liang; Lin,Yu Chang; Lin,Yu Ting, Apparatus and method for testing conductive bumps.
  6. Cram,Daniel P., Apparatus for deforming resilient contact structures on semiconductor components.
  7. Yojima Masayuki,JPX ; Tsujide Tohru,JPX ; Nakaizumi Kazuo,JPX, Apparatus for testing semiconductor wafer.
  8. DeHaven, Robert Keith; Wenzel, James F., Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer.
  9. Haulin Tord L.,SEX, Assembly and method for testing integrated circuit devices.
  10. Burtzlaff,Robert; Haba,Belgacem; Humpston,Giles; Tuckerman,David B.; Warner,Michael; Mitchell,Craig S., Back-face and edge interconnects for lidded package.
  11. Miller, Charles A., Bi-directional buffer for interfacing test system channel.
  12. Matsumura,Shigeru, Bump and method of forming bump.
  13. Hashimoto, Osamu, Burn-in apparatus having average voltage calculating circuit.
  14. Kolman,Robert S., Carousel device, system and method for electronic circuit tester.
  15. Ruffler, Jens, Chemical removal of oxide layer from chip pads.
  16. Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Chip with sintered connections to package.
  17. Dunklee, John, Chuck for holding a device under test.
  18. Dunklee, John, Chuck for holding a device under test.
  19. Dunklee, John, Chuck for holding a device under test.
  20. Dunklee,John, Chuck for holding a device under test.
  21. Dunklee,John, Chuck for holding a device under test.
  22. Dunklee,John, Chuck for holding a device under test.
  23. Stewart, Craig; Lord, Anthony; Spencer, Jeff; Burcham, Terry; McCann, Peter; Jones, Rod; Dunklee, John; Lesher, Tim; Newton, David, Chuck for holding a device under test.
  24. Stewart,Craig; Lord,Anthony; Spencer,Jeff; Burcham,Terry; McCann,Peter; Jones,Rod; Dunklee,John; Lesher,Tim; Newton,David, Chuck for holding a device under test.
  25. Andrews, Peter; Froemke, Brad; Dunklee, John, Chuck with integrated wafer support.
  26. Andrews,Peter; Froemke,Brad; Dunklee,John, Chuck with integrated wafer support.
  27. Andrews,Peter; Froemke,Brad; Dunklee,John, Chuck with integrated wafer support.
  28. Poehl, Frank; Rzeha, Jan; Beck, Matthias; Goessel, Michael; Muhmenthaler, Peter, Circuit for compression and storage of circuit diagnosis data.
  29. Adler, Frank; Berger, Hartmut, Circuit for testing an integrated circuit.
  30. Fjelstad, Joseph, Compliant package with conductive elastomeric posts.
  31. Legal Dennis Andrew, Configurable probe card for automatic test equipment.
  32. Mok, Sammy; Chong, Fu Chiung, Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies.
  33. Khandros,Igor Y., Contact structures and methods for making same.
  34. Haley Mark W. (San Antonio TX) Sparks Eric A. (San Antonio TX), Converter and digital channel selector.
  35. Furukawa,Yasuo, Device and method for electronic device test.
  36. Cowan, Joseph W., Device under interface card with on-board testing.
  37. Richard S. Roy ; Charles A. Miller, Distributed interface for parallel testing of multiple devices using a single tester channel.
  38. Roy, Richard S.; Miller, Charles A., Distributed interface for parallel testing of multiple devices using a single tester channel.
  39. Charles A. Miller ; Richard S. Roy, Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses.
  40. Miller, Charles A.; Roy, Richard S., Efficient parallel testing of semiconductor devices using a known good device to generate expected responses.
  41. Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Electrochemical fabrication process for forming multilayer multimaterial microprobe structures.
  42. Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Electrochemical fabrication process for forming multilayer multimaterial microprobe structures.
  43. Arat,Vacit; Cohen,Adam L.; Smalley,Dennis R.; Kruglick,Ezekiel J. J.; Chen,Richard T.; Kim,Kieun, Electrochemically fabricated microprobes.
  44. Haemer,Joseph Michael; Chong,Fu Chiung; Modlin,Douglas N., Enhanced compliant probe card systems having improved planarity.
  45. Ban, Naoto; Namba, Masaaki; Hasebe, Akio; Wada, Yuji; Kohno, Ryuji; Seito, Akira; Motoyama, Yasuhiro, Fabrication method of semiconductor integrated circuit device and its testing apparatus.
  46. Cohen, Adam L.; Arat, Vacit; Lockard, Michael S.; Bang, Christopher A.; Lembrikov, Pavel B., Fabrication process for co-fabricating multilayer probe array and a space transformer.
  47. Eldridge, Benjamin N.; Khandros, Igor Y., Fan out of interconnect elements attached to semiconductor wafer.
  48. Johnson,Morgan T., Full wafer contacter and applications thereof.
  49. Dunklee, John; Norgden, Greg; Cowan, C. Eugene, Guarded tub enclosure.
  50. Dunklee,John; Norgden,Greg; Cowan,C. Eugene, Guarded tub enclosure.
  51. Whetsel, Lee D., Hierarchical linking module connection to access ports of embedded cores.
  52. Bottoms, Wilmer R.; Chong, Fu Chiung; Mok, Sammy; Modlin, Douglas, High density interconnect system for IC packages and interconnect assemblies.
  53. Chong, Fu Chiung; Kao, Andrew; McKay, Douglas; Litza, Anna; Modlin, Douglas; Mok, Sammy; Parekh, Nitin; Swiatowiec, Frank John; Shan, Zhaohui, High density interconnect system having rapid fabrication cycle.
  54. Chong, Fu Chiung; Kao, Andrew; McKay, Douglas; Litza, Anna; Modlin, Douglas; Mok, Sammy; Parekh, Nitin; Swiatowiec, Frank John; Shan, Zhaohui, High density interconnect system having rapid fabrication cycle.
  55. Chong,Fu Chiung; Kao,Andrew; McKay,Douglas; Litza,Anna; Modlin,Douglas; Mok,Sammy; Parekh,Nitin; Swiatowiec,Frank John; Shan,Zhaohui, High density interconnect system having rapid fabrication cycle.
  56. Warner, Michael, High-frequency chip packages.
  57. Whetsel, Lee D., IC with shared scan cells selectively connected in scan path.
  58. Fjelstad, Joseph; Karavakis, Konstantine, Image forming apparatus with improved transfer efficiency.
  59. Shinozaki,Dai; Komatsu,Shigekazu, Inspection method and inspection equipment.
  60. Walter, Fabrice; Ratajczak, Christophe, Integrated circuit provided with means for calibrating an electronic module and method for calibrating an electronic module of an integrated circuit.
  61. C. Patrick Doherty ; Jorge L. deVarona ; Salman Akram, Interconnect and system for testing bumped semiconductor components with on-board multiplex circuitry for expanding tester resources.
  62. C. Patrick Doherty ; Jorge L. deVarona ; Salman Akram, Interconnect and system for testing bumped semiconductor components with on-board multiplex circuitry for expanding tester resources.
  63. Eldridge, Benjamin N.; Mathieu, Gaetan, Interconnect assemblies and methods.
  64. Strid, Eric W.; Schappacher, Jerry B.; Carlton, Dale E.; Gleason, K. Reed, Interconnect assembly for use in evaluating probing networks.
  65. Andrews, Peter; Hess, David; New, Robert, Interface for testing semiconductors.
  66. Lee, Sang-hoon; Ko, Chang-woo; An, Young-soo; Oh, Se-jang, Interface structure of wafer test equipment.
  67. Leung,Omar S., Interleaved MEMS-based probes for testing integrated circuits.
  68. Miller, Charles A., Isolation buffers with controlled equal time delays.
  69. Miller,Charles A., Isolation buffers with controlled equal time delays.
  70. Miller,Charles A., Isolation buffers with controlled equal time delays.
  71. Pedersen, David V.; Khandros, Igor Y., Lithographically defined microelectronic contact structures.
  72. McFadden,Bruce, Localizing a temperature of a device for testing.
  73. Davidson, Colin, Low stress test mode.
  74. Chong, Fu Chiung; Mok, Sammy, Massively parallel interface for electronic circuit.
  75. Chong,Fu Chiung; Mok,Sammy, Massively parallel interface for electronic circuit.
  76. Chong,Fu Chiung; Mok,Sammy, Massively parallel interface for electronic circuit.
  77. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Method and apparatus for burning-in semiconductor devices in wafer form.
  78. Marcuse, Arno G.; Most, Robert A.; North, Edward S., Method and apparatus for cleaning electronic test contacts.
  79. Dastidar, Jayabrata Ghosh; Beni, Aman Aflaki; Kasnavi, Zunhang Yu, Method and apparatus for die testing.
  80. Slupsky, Steven; Sellathamby, Chistopher, Method and apparatus for interrogating an electronic component.
  81. Slupsky, Steven; Sellathamby, Christopher, Method and apparatus for interrogating an electronic component.
  82. Leedy Glenn, Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus.
  83. Kemmerling, Todd Ryland, Method and apparatus for processing failures during semiconductor device testing.
  84. Berry, Tommie Edward; Sporck, Alistair Nicholas, Method and apparatus for testing devices using serially controlled intelligent switches.
  85. Berry, Tommie Edward; Sporck, Alistair Nicholas, Method and apparatus for testing devices using serially controlled intelligent switches.
  86. Berry, Tommie Edward, Method and apparatus for testing devices using serially controlled resources.
  87. Kemmerling, Todd Ryland, Method and apparatus for testing semiconductor devices with autonomous expected value generation.
  88. Doong, Yih-Yuh; Cheng, Jye-Yen; Charles, Ching-Hsiang Hsu, Method and device for addressable failure site test structure.
  89. H?bner, Michael; Krause, Gunnar; Kuhn, Justus; M?ller, Jochen; P{hacek over (o)}chm?ller, Peter; Weidenh?fer, J?rgen, Method and probe card configuration for testing a plurality of integrated circuits in parallel.
  90. Leedy, Glenn, Method and system for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus.
  91. Cram, Daniel P., Method and system for wafer level testing and burning-in semiconductor components.
  92. Doherty, C. Patrick; Akram, Salman; de Varona, Jorge L., Method and system having switching network for testing semiconductor components on a substrate.
  93. Doherty, C. Patrick; de Varona, Jorge L.; Akram, Salman, Method and system having switching network for testing semiconductor components on a substrate.
  94. DeHaven Robert Keith (Austin TX) Wenzel James F. (Austin TX), Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located.
  95. Khandros Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  96. Khandros, Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  97. Khandros, Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  98. Eldridge,Benjamin N.; Grube,Gary W.; Khandros,Igor Y.; Mathieu,Gaetan L., Method for mounting a plurality of spring contact elements.
  99. Robert Keith DeHaven ; James F. Wenzel, Method for testing a product integrated circuit wafer using a stimulus integrated circuit wafer.
  100. Hembree, David R.; Farnworth, Warren M.; Akram, Salman; Wood, Alan G.; Doherty, C. Patrick; Krivy, Andrew J., Method for testing semiconductor wafers.
  101. Wood,Alan G.; Corbett,Tim J., Method for testing using a universal wafer carrier for wafer level die burn-in.
  102. Wood,Alan G.; Corbett,Tim J., Method for testing using a universal wafer carrier for wafer level die burn-in.
  103. Wood,Alan G.; Corbett,Tim J., Method for testing using a universal wafer carrier for wafer level die burn-in.
  104. Wood,Alan G.; Corbett,Tim J., Method for testing using a universal wafer carrier for wafer level die burn-in.
  105. Wood,Alan G.; Corbett,Tim J., Method for testing using a universal wafer carrier for wafer level die burn-in.
  106. Wood,Alan G.; Corbett,Tim J., Method for testing using a universal wafer carrier for wafer level die burn-in.
  107. Strid Eric W. (Portland OR) Schappacher Jerry B. (Portland OR) Carlton Dale E. (Portland OR) Gleason K. Reed (Portland OR), Method of evaluating signal conditions in a probe measurement network having a plurality of separate measurement channel.
  108. Nulty, James E.; Hunter, James A.; Herrera, Alexander J., Method of fabricating a probe card.
  109. Kim,Kieun; Cohen,Adam L.; Larsen,Willa M.; Chen,Richard T.; Kumar,Ananda H.; Kruglick,Ezekiel J. J.; Arat,Vacit; Zhang,Gang; Lockard,Michael S., Method of making a contact.
  110. Eldridge,Benjamin Niles; Grube,Gary William; Khandros,Igor Yan; Mathieu,Gaetan L., Method of making a contact structure with a distinctly formed tip structure.
  111. Benjamin N. Eldridge ; Gary W. Grube ; Igor Y. Khandros ; Gaetan L. Mathieu, Method of making microelectronic contact structures.
  112. Khandros Igor Y., Method of mounting free-standing resilient electrical contact structures to electronic components.
  113. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of mounting resilient contact structures to semiconductor devices.
  114. Lee,Sang Hoon; Ji,Joon Su; Ahn,Jung Bae, Method of performing parallel test on semiconductor devices by dividing voltage supply unit.
  115. Budnaitis John J. ; Leong Jimmy, Method of wafer level burn-in.
  116. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Method of wirebonding that utilizes a gas flow within a capillary from which a wire is played out.
  117. Zilber, Gil; Katraro, Reuven; Aksenton, Julia; Oganesian, Vage, Methods and apparatus for packaging integrated circuit devices.
  118. Zilber,Gil; Aksenton,Julia; Oganesian,Vage, Methods and apparatus for packaging integrated circuit devices.
  119. Zilber,Gil; Aksenton,Julia; Oganesian,Vage, Methods and apparatus for packaging integrated circuit devices.
  120. Zilber,Gil; Katraro,Reuven; Aksenton,Julia; Oganesian,Vage, Methods and apparatus for packaging integrated circuit devices.
  121. Fjelstad, Joseph, Methods and structures for electronic probing arrays.
  122. Fjelstad, Joseph, Methods and structures for electronic probing arrays.
  123. Fjelstad, Joseph; Smith, John W., Methods and structures for electronic probing arrays.
  124. Joseph Fjelstad, Methods and structures for electronic probing arrays.
  125. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Methods of creating probe structures from a plurality of planar layers.
  126. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Methods of creating probe structures from a plurality of planar layers.
  127. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Methods of creating probe structures from a plurality of planar layers.
  128. Fjelstad, Joseph; Karavakis, Konstantine, Methods of making compliant semiconductor chip packages.
  129. DiStefano Thomas H. ; Solberg Vernon, Methods of making microelectronic assemblies.
  130. Kovac,Zlata; Mitchell,Craig S.; DiStefano,Thomas H.; Smith,John W., Methods of making microelectronic assemblies including compliant interfaces.
  131. Fjelstad,Joseph, Methods of making microelectronic packages with conductive elastomeric posts.
  132. Khandros Igor Y. ; DiStefano Thomas H., Methods of making semiconductor chip assemblies.
  133. Benjamin, Neil, Methods relating to wafer integrated plasma probe assembly arrays.
  134. Haba, Belgacem, Microelectronic assemblies having compliancy.
  135. Oganesian, Vage; Gao, Guilian; Haba, Belgacem; Ovrutsky, David, Microelectronic assemblies having compliancy and methods therefor.
  136. Oganesian, Vage; Gao, Guilian; Haba, Belgacem; Ovrutsky, David, Microelectronic assemblies having compliancy and methods therefor.
  137. Oganesian, Vage; Gao, Guilian; Haba, Belgacem; Ovrutsky, David, Microelectronic assemblies having compliancy and methods therefor.
  138. Fjelstad, Joseph; Karavakis, Konstantine, Microelectronic assemblies having compliant layers.
  139. Fjelstad, Joseph; Karavakis, Konstantine, Microelectronic assemblies having compliant layers.
  140. Fjelstad,Joseph; Karavakis,Konstantine, Microelectronic assemblies having compliant layers.
  141. Fjelstad,Joseph; Karavakis,Konstantine, Microelectronic assemblies having compliant layers.
  142. Nystrom, Michael J.; Humpston, Giles, Microelectronic assembly with multi-layer support structure.
  143. Nystrom, Michael J.; Humpston, Giles, Microelectronic assembly with multi-layer support structure.
  144. Gilleo Kenneth B. ; Karavakis Konstantine, Microelectronic component mounting with deformable shell terminals.
  145. Gilleo Kenneth B. ; Karavakis Konstantine, Microelectronic component mounting with deformable shell terminals.
  146. DiStefano Thomas H. ; Solberg Vernon, Microelectronic connections with solid core joining units.
  147. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
  148. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
  149. Fjelstad, Joseph; Karavakis, Konstantine, Microelectronic package having a compliant layer with bumped protrusions.
  150. Benjamin N. Eldridge ; Gary W. Grube ; Igor Y. Khandros ; Gaetan L. Mathieu, Microelectronic spring contact element and electronic component having a plurality of spring contact elements.
  151. Kim,Kieun; Cohen,Adam L.; Larsen,Willa M.; Chen,Richard T.; Kumar,Ananda H.; Kruglick,Ezekiel J. J.; Arat,Vacit; Zhang,Gang; Lockard,Michael S., Microprobe tips and methods for making.
  152. Kim,Kieun; Cohen,Adam L.; Larsen,Willa M.; Chen,Richard T.; Kumar,Ananda H.; Kruglick,Ezekiel J. J.; Arat,Vacit; Zhang,Gang; Lockard,Michael S.; Bang,Christopher A., Microprobe tips and methods for making.
  153. Cheng, Shih-Jye; Liu, An-Hong; Wang, Yeong-Her; Chao, Yeong-Ching; Lee, Yao-Jung, Modularized probe head.
  154. Eldridge,Benjamin N.; Grube,Gary W.; Khandros,Igor Y.; Mathieu,Gaetan L., Mounting spring elements on semiconductor devices, and wafer-level testing methodology.
  155. Frisch Arnold M., Multi-chip module development substrate.
  156. Sun,Horng Chuan; Yang,Hui Pin, Multi-function probe card.
  157. Wu, Ming Ting; Larsen, III, Rulon Joseph; Kim, Young; Kim, Kieun; Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Multi-layer, multi-material fabrication methods for producing micro-scale and millimeter-scale devices with enhanced electrical and/or mechanical properties.
  158. Wu, Ming Ting; Larsen, III, Rulon J.; Kim, Young; Kim, Kieun; Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Multi-layer, multi-material micro-scale and millimeter-scale devices with enhanced electrical and/or mechanical properties.
  159. Wu, Ming Ting; Larsen, III, Rulon J.; Kim, Young; Kim, Kieun; Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Multi-layer, multi-material micro-scale and millimeter-scale devices with enhanced electrical and/or mechanical properties.
  160. Shin, Young-Gu; Heo, Kyoung-Il; Lee, Hyoung-Young; Kwon, Hyuk; Ju, Ki-Bong; Bang, Jeong-Ho; Shim, Hyun-Seop, Multichip package test.
  161. Shin,Young Gu; Heo,Kyoung Il; Lee,Hyoung Young; Kwon,Hyuk; Ju,Ki Bong; Bang,Jeong Ho; Shim,Hyun Seop, Multichip package test.
  162. Lo, Tseng-Chin; Tseng, Huan Chi; Chang, Kuo-Chuan; Chang, Yuan-Yao; Lee, Chien-Chang, Multidirectional semiconductor arrangement testing.
  163. Noguchi Etsuo (Mitaka JPX), Multiprobing semiconductor test method for testing a plurality of chips simultaneously.
  164. Harris,Daniel L.; McCann,Peter R., Optical testing device.
  165. Richard S. Roy ; Charles A. Miller, Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons.
  166. Lee, Sang Hoon; Ji, Joon Su; Ahn, Jung Bae, Parallel testing of semiconductor devices using a dividing voltage supply unit.
  167. Bergman Reuter, Betty L.; DeHond, Mitchell R.; Leipold, William C.; Maynard, Daniel N.; Pfeifer, Brian D.; Reynolds, David C.; Wilcox, Jr., Reginald B., Physical design characterization system.
  168. Whetsel, Lee D., Position independent testing of circuits.
  169. Eldridge, Benjamin N.; Miller, Charles A., Predictive, adaptive power supply for an integrated circuit under test.
  170. Eldridge,Benjamin N.; Miller,Charles A., Predictive, adaptive power supply for an integrated circuit under test.
  171. Nakata, Yoshiro; Oki, Shinichi; Ishizaka, Masaaki, Probe card.
  172. David R. Hembree ; Warren M. Farnworth ; Salman Akram ; Alan G. Wood ; C. Patrick Doherty ; Andrew J. Krivy, Probe card and test system for semiconductor wafers.
  173. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Probe card assembly.
  174. Khandros, Jr., Igor Y.; Sporck, Jr., A. Nicholas; Eldridge, Jr., Benjamin N., Probe card assembly.
  175. Khandros,Igor Y.; Sporck,A. Nicholas; Eldridge,Benjamin N., Probe card assembly.
  176. Eldridge, Benjamin N.; Khandros, Igor Y.; Sporck, A. Nicholas, Probe card assembly and kit.
  177. Khandros,Igor Y.; Sporck,A. Nicholas; Eldridge,Benjamin N., Probe card assembly and kit.
  178. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Probe card assembly and kit, and methods of making same.
  179. Eldridge, Benjamin Niles; Grube, Gary William; Khandros, Igor Yan; Mathieu, Gaetan L., Probe card assembly and kit, and methods of making same.
  180. Eldridge, Benjamin N.; Grube, Gary W.; Mathieu, Gaetan L., Probe card assembly for contacting a device with raised contact elements.
  181. Mathieu, Gaetan L.; Eldridge, Benjamin N.; Grube, Gary W., Probe card assembly having an actuator for bending the probe substrate.
  182. Kim, Min-gu; Choi, Ho-jeong; An, Young-soo, Probe card capable of multi-probing.
  183. Hembree,David R.; Farnworth,Warren M.; Akram,Salman; Wood,Alan G.; Doherty,C. Patrick; Krivy,Andrew J., Probe card for semiconductor wafers having mounting plate and socket.
  184. Momohara, Tomomi, Probe card having groups of probe needles in a probing test apparatus for testing semiconductor integrated circuits.
  185. Momohara,Tomomi, Probe card having groups of probe needles in a probing test apparatus for testing semiconductor integrated circuits.
  186. C. Patrick Doherty ; Jorge L. deVarona ; Salman Akram, Probe card having on-board multiplex circuitry for expanding tester resources.
  187. Doherty C. Patrick ; deVarona Jorge L. ; Akram Salman, Probe card having on-board multiplex circuitry for expanding tester resources.
  188. Sporck, A. Nicholas; Shinde, Makarand S., Probe card with coplanar daughter card.
  189. Sporck,Alistair Nicholas; Shinde,Makarand S., Probe card with coplanar daughter card.
  190. Chen, Richard T.; Kruglick, Ezekiel J. J.; Bang, Christopher A.; Smalley, Dennis R.; Lembrikov, Pavel B., Probe devices formed from multiple planar layers of structural material with tip regions formed from one or more intermediate planar layers.
  191. Rogers, Gary; Clauter, Steve; Schwartz, Rodney; Ukai, Taichi; Lambright, Joe; Lohr, Dave, Probe needle protection method for high current probe testing of power devices.
  192. Nordgren, Greg; Dunklee, John, Probe station.
  193. Nordgren, Greg; Dunklee, John, Probe station.
  194. Peters, Ron A.; Hayden, Leonard A.; Hawkins, Jeffrey A.; Dougherty, R. Mark, Probe station having multiple enclosures.
  195. Peters,Ron A.; Hayden,Leonard A.; Hawkins,Jeffrey A.; Dougherty,R. Mark, Probe station having multiple enclosures.
  196. Peters,Ron A.; Hayden,Leonard A.; Hawkins,Jeffrey A.; Dougherty,R. Mark, Probe station having multiple enclosures.
  197. Cowan, Clarence E.; Tervo, Paul A.; Dunklee, John L., Probe station thermal chuck with shielding for capacitive current.
  198. Cowan,Clarence E.; Tervo,Paul A.; Dunklee,John L., Probe station thermal chuck with shielding for capacitive current.
  199. Cowan,Clarence E.; Tervo,Paul A.; Dunklee,John L., Probe station thermal chuck with shielding for capacitive current.
  200. Dunklee,John; Cowan,Clarence E., Probe station with low inductance path.
  201. Dunklee,John; Cowan,Clarence E., Probe station with low inductance path.
  202. Lesher, Timothy; Miller, Brad; Cowan, Clarence E.; Simmons, Michael; Gray, Frank; McDonald, Cynthia L., Probe station with low noise characteristics.
  203. Lesher,Timothy; Miller,Brad; Cowan,Clarence E.; Simmons,Michael; Gray,Frank; McDonald,Cynthia L., Probe station with low noise characteristics.
  204. Lesher,Timothy; Miller,Brad; Cowan,Clarence E.; Simmons,Michael; Gray,Frank; McDonald,Cynthia L., Probe station with low noise characteristics.
  205. Navratil,Peter; Froemke,Brad; Stewart,Craig; Lord,Anthony; Spencer,Jeff; Runbaugh,Scott; Fisher,Gavin; McCann,Pete; Jones,Rod, Probe station with two platens.
  206. Cho, Dong-il; Park, Sangjun, Probe structure for testing semiconductor devices and method for fabricating the same.
  207. Lesher, Timothy E., Probe testing structure.
  208. Lesher,Timothy E., Probe testing structure.
  209. Jin,Bo; Gu,Qi, Proble for testing integrated circuits.
  210. Gaggl,Rainer, Process and circuit for protection of test contacts in high current measurement of semiconductor components.
  211. Wood Alan G. (Boise ID) Doan Trung T. (Boise ID) Farnworth Warren M. (Nampa ID) Corbett Tim J. (Boise ID), Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor.
  212. Whetsel Lee D., Process of selecting dies for testing on a wafer.
  213. Whetsel, Lee D., Process of testing a semiconductor wafer of IC dies.
  214. Vogley, Wilbur C., Reduced cost, high speed circuit test arrangement.
  215. Vogley, Wilbur C., Reduced cost, high speed integrated circuit test arrangement.
  216. Farnworth Warren M. ; Nevill Leland R. ; Beffa Raymond J. ; Cloud Eugene H., Reduced terminal testing system.
  217. Farnworth Warren M. ; Nevill Leland R. ; Beffa Raymond J. ; Cloud Eugene H., Reduced terminal testing system.
  218. Farnworth Warren M. ; Nevill Leland R. ; Beffa Raymond J. ; Cloud Eugene H., Reduced terminal testing system.
  219. Farnworth Warren M. ; Nevill Leland R. ; Beffa Raymond J. ; Cloud Eugene H., Reduced terminal testing system.
  220. Farnworth, Warren M.; Nevill, Leland R.; Beffa, Raymond J.; Cloud, Eugene H., Reduced terminal testing system.
  221. Farnworth, Warren M.; Nevill, Leland R.; Beffa, Raymond J.; Cloud, Eugene H., Reduced terminal testing system.
  222. Farnworth, Warren M.; Nevill, Leland R.; Beffa, Raymond J.; Cloud, Eugene H., Reduced terminal testing system.
  223. Warren M. Farnworth ; Leland R. Nevill ; Raymond J. Beffa ; Eugene H. Cloud, Reduced terminal testing system.
  224. Strid, Eric W.; Schappacher, Jerry B.; Carlton, Dale E.; Gleason, K. Reed, Reference transmission line junction for probing device.
  225. Davis Richard P. ; Chen Jiann-Neng, Relayless voltage measurement in automatic test equipment.
  226. Salmon,Peter C., Repairable three-dimensional semiconductor subsystem.
  227. Eldridge, Benjamin N.; Henson, Roy J.; Hobbs, Eric D.; Mathews, Peter B.; Shinde, Makarand S., Sawing tile corners on probe card substrates.
  228. Salmon, Peter C., Scalable subsystem architecture having integrated cooling channels.
  229. Whetsel, Lee D., Scan circuit low power adapter with counter.
  230. Whetsel,Lee D.; Haroun,Baher S.; Lasher,Brian J.; Kinra,Anjali, Selecting different 1149.1 TAP domains from update-IR state.
  231. Schaeffer,Ralph; Crump,Brett, Selectively configurable probe structures, e.g., for testing microelectronic components.
  232. Schaeffer,Ralph; Crump,Brett, Selectively configurable probe structures, e.g., selectively configurable probe cards for testing microelectronic components.
  233. Takeuchi, Nobuaki, Semiconductor test apparatus with reduced power consumption and heat generation.
  234. Thompson Patrick F. (Chandler AZ) Williams William M. (Gilbert AZ) Lindsey Scott E. (Mesa AZ) Vasquez Barbara (Austin TX), Semiconductor wafer contact system and method for contacting a semiconductor wafer.
  235. Nakata Yoshirou,JPX ; Yamada Toshio,JPX ; Fujiwara Atsushi,JPX ; Miyanaga Isao,JPX ; Hashimoto Shin,JPX ; Uraoka Yukiharu,JPX ; Okuda Yasushi,JPX ; Hatada Kenzou,JPX, Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and .
  236. James Marc Leas ; Robert William Koss ; Jody John Van Horn ; George Frederick Walker ; Charles Hampton Perry ; David Lewis Gardell ; Steve Leo Dingle ; Ronald Prilik, Semiconductor wafer test and burn-in.
  237. Leas James Marc ; Koss Robert William ; Van Horn Jody John ; Walker George Frederick ; Perry Charles Hampton ; Gardell David Lewis ; Dingle Steve Leo ; Prilik Ronald, Semiconductor wafer test and burn-in.
  238. Watanabe, Daisuke; Okayasu, Toshiyuki, Semiconductor wafer, semiconductor circuit, substrate for testing and test system.
  239. Honer, Kenneth Allen, Sequential fabrication of vertical conductive interconnects in capped chips.
  240. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Madsen, Alex; Mathieu, Gaetan L., Sharpened, oriented contact tip structures.
  241. Murphy Adrian ; Thavarajah Manickam, Silicon wafer or die strength test fixture using high pressure fluid.
  242. Sobolewski Gregory ; Klubert Lawrence M., Source measure unit current preamplifier.
  243. Humpston,Giles, Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps.
  244. McWilliams,Bruce M.; Humpston,Giles; Haba,Belgacem; Tuckerman,David B., Structure and method of making sealed capped chips.
  245. Dunklee,John, Switched suspended conductor and connection.
  246. Dunklee,John, Switched suspended conductor and connection.
  247. Strid,Eric W.; Schappacher,Jerry B.; Carlton,Dale E.; Gleason,K. Reed, System for evaluating probing networks.
  248. Strid,Eric W.; Schappacher,Jerry B.; Carlton,Dale E.; Gleason,K. Reed, System for evaluating probing networks.
  249. Strid,Eric W.; Schappacher,Jerry B.; Carlton,Dale E.; Gleason,K. Reed, System for evaluating probing networks.
  250. Leedy, Glenn, System for probing, testing, burn-in, repairing and programming of integrated circuits.
  251. C. Patrick Doherty ; Jorge L. deVarona ; Salman Akram, System for testing bumped semiconductor components with on-board multiplex circuit for expanding tester resources.
  252. Andrews, Peter; Hess, David, System for testing semiconductors.
  253. Mok, Sammy; Chong, Fu Chiung; Milter, Roman, Systems for testing and packaging integrated circuits.
  254. Negishi, Kazuki; Hansen, Mark, Test apparatus for measuring a characteristic of a device under test.
  255. Hartmann,Udo; Canaud,Thierry, Test arrangement for testing semiconductor circuit chips.
  256. Eldridge, Benjamin N.; Khandros, Igor Y.; Pedersen, David V.; Whitten, Ralph G., Test assembly including a test die for testing a semiconductor product die.
  257. Eldridge, Benjamin N.; Khandros, Igor Y.; Pedersen, David V.; Whitten, Ralph G., Test assembly including a test die for testing a semiconductor product die.
  258. Eldridge, Benjamin N.; Khandros, Igor Y.; Pedersen, David V.; Whitten, Ralph G., Test assembly including a test die for testing a semiconductor product die.
  259. Hembree, David R.; Akram, Salman; Farnworth, Warren M.; Wood, Alan G.; Gochnour, Derek; Jacobson, John O.; Wark, James M.; Ahmad, Syed Sajid, Test carrier with molded interconnect for testing semiconductor components.
  260. Nikutta Wolfgang,DEX ; Schmokel Hartmut,DEX ; Kuchinke Gunther,DEX ; von der Ropp Thomas,DEX ; Walter Rudolph, Test circuit and testing method for function testing of electronic circuits.
  261. Hübner, Michael; Krause, Gunnar; Kuhn, Justus; Müller, Jochen; Pöchmüller, Peter; Weidenhöfer, Jürgen, Test configuration and test method for testing a plurality of integrated circuits in parallel.
  262. Bucksch,Thorsten, Test device for wafer testing digital semiconductor circuits.
  263. Shimizu, Isao; Sato, Masayuki; Fukiage, Hiroshi, Test system and manufacturing of semiconductor device.
  264. Vogley Wilbur C., Test system and process with microcomputers and serial interface.
  265. Yamada,Masuhiro; Sato,Kazuhiko; Ohsawa,Toshimi, Testing apparatus and testing method.
  266. Takashi Sato JP, Testing apparatus for test piece testing method contactor and method of manufacturing the same.
  267. Sato, Takashi, Testing apparatus for test piece, testing method, contactor and method of manufacturing the same.
  268. Rumbaugh,Scott, Thermal optical chuck.
  269. Rumbaugh,Scott, Thermal optical chuck.
  270. Ilani Avner,ILX, Universal fixtureless test equipment.
  271. Wood,Alan G.; Corbett,Tim J., Universal wafer carrier for wafer level die burn-in.
  272. Wood,Alan G.; Corbett,Tim J., Universal wafer carrier for wafer level die burn-in.
  273. Wood,Alan G.; Corbett,Tim J.; Farnworth,Warren M., Universal wafer carrier for wafer level die burn-in.
  274. Verkuil Roger L. ; Kleefstra Meindert J., Vacuum activated backside contact.
  275. Eldridge,Benjamin N.; Mathieu,Gaetan, Variable width resilient conductive contact structures.
  276. Doong,Yih Yuh, Versatile semiconductor test structure array.
  277. Benjamin, Neil, Wafer integrated plasma probe assembly array.
  278. Benjamin, Neil, Wafer integrated plasma probe assembly array.
  279. Schwindt, Randy J.; Harwood, Warren K.; Tervo, Paul A.; Smith, Kenneth R.; Warner, Richard H., Wafer probe station having a skirting component.
  280. Schwindt,Randy J.; Harwood,Warren K.; Tervo,Paul A.; Smith,Kenneth R.; Warner,Richard H., Wafer probe station having a skirting component.
  281. Schwindt,Randy J.; Harwood,Warren K.; Tervo,Paul A.; Smith,Kenneth R.; Warner,Richard H., Wafer probe station having a skirting component.
  282. Harwood, Warren K.; Tervo, Paul A.; Koxxy, Martin J., Wafer probe station having environment control enclosure.
  283. Harwood,Warren K.; Tervo,Paul A.; Koxxy,Martin J., Wafer probe station having environment control enclosure.
  284. Doherty C. Patrick ; deVarona Jorge L. ; Akram Salman, Wafer test method with probe card having on-board multiplex circuitry for expanding tester resources.
  285. Khandros, Igor Y.; Pedersen, David V., Wafer-level burn-in and test.
  286. Khandros, Igor Y.; Pedersen, David V., Wafer-level burn-in and test.
  287. Khandros,Igor Y.; Pedersen,David V., Wafer-level burn-in and test.
  288. Khandros,Igor Y.; Pedersen,David V., Wafer-level burn-in and test.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트