이 특허를 인용한 특허 (187)

1. Bedeschi,Ferdinando; Resta,Claudio, Biasing circuit for use in a non-volatile memory device.

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2. Sobek Daniel ; Thurgate Timothy James ; Luning Scott D. ; Chan Vei-Han ; Haddad Sameer S., Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices.

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3. Sobek Daniel ; Thurgate Timothy James ; Luning Scott D. ; Chan Vei-Han ; Haddad Sameer S., Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices.

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4. Lakhani Vinod, Bitline disturb reduction.

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5. Shiau Tzeng-Huei,TWX ; Lin Yu-Shen,TWX ; Wan Ray-Lin, Block decoded wordline driver with positive and negative voltage modes.

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6. Yiu Tom D. ; Lee I-Long,TWX ; Chang Kuen-Long,TWX ; Chen Han-Sung,TWX ; Shiau Tzeng-Huei,TWX ; Hung Chun-Hsiung,TWX ; Wan Ray-Lin, Block-level wordline enablement to reduce negative wordline stress.

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7. Cappelletti Paolo (Seveso ITX) Casagrande Giulio (Vignate ITX), Byte erasable EEPROM fully compatible with a single power supply flash-EPROM process.

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8. Choi Byeng-Sun,KRX, Common source line control circuit for preventing snap back breakdown.

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9. Van Houdt Jan F.,BEX ; Groeseneken Guido,BEX ; Maes Herman,BEX, Contacted cell array configuration for erasable and programmable semiconductor memories.

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10. Van Houdt Jan F.,BEX ; Groeseneken Guido,BEX ; Maes Herman,BEX, Contactless array configuration for semiconductor memories.

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11. Fujiwara, Hideaki, Coupling coefficient measuring method and coupling coefficient measuring apparatus for semiconductor memory.

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12. Shalvi, Ofir; Winter, Shai; Sommer, Naftali; Sokolov, Dotan, Data storage in analog memory cell arrays having erase failures.

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13. Takuji Yoshida JP, EEPROM erasing method.

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14. Takuji Yoshida JP, EEPROM erasing method.

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15. Yoshida, Takuji, EEPROM erasing method.

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16. Brigati Alessandro,FRX ; Demange Nicolas,FRX ; Aulas Maxence,FRX ; Guedj Marc,FRX, EEPROM memory programmable and erasable by Fowler-Nordheim effect.

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17. Yoshida,Takuji, EEPROM writing and reading method.

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18. Yoshida, Takuji, EEPROM writing method.

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19. Tempel Georg,DEX ; Winnerl Josef,DEX, Electrically erasable and programmable non-volatile storage location.

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20. Kobayashi Shinichi (Hyogo-ken JPX) Terada Yasushi (Hyogo-ken JPX) Miyawaki Yoshikazu (Hyogo-ken JPX) Nakayama Takeshi (Hyogo-ken JPX) Futatsuya Tomoshi (Hyogo-ken JPX) Ajika Natsuo (Hyogo-ken JPX) Ku, Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor.

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21. Kobayashi Shinichi,JPX ; Terada Yasushi,JPX ; Miyawaki Yoshikazu,JPX ; Nakayama Takeshi,JPX ; Futatsuya Tomoshi,JPX ; Ajika Natsuo,JPX ; Kunori Yuichi,JPX ; Onoda Hiroshi,JPX ; Fukumoto Atsushi,JPX ;, Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor.

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22. Kobayashi Shinichi,JPX ; Terada Yasushi,JPX ; Miyawaki Yoshikazu,JPX ; Nakayama Takeshi,JPX ; Futatsuya Tomoshi,JPX ; Ajika Natsuo,JPX ; Kunori Yuichi,JPX ; Onoda Hiroshi,JPX ; Fukumoto Atsushi,JPX ;, Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor.

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23. Hsu Fu-Chang ; Tsao Hsing-Ya ; Lee Peter W. ; Chan Vei-Han ; Chen Hung-Sheng, Erase condition for flash memory.

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24. Wang, Arthur; Young, Jein-Chen; Kwan, Ming, Erase method for flash memory.

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25. Jinbo Toshikatsu,JPX, Erasing method and erasing device for non-volatile semiconductor memory.

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26. Sharma Umesh (Austin TX) Chang Kuo-Tung (Austin TX), Fabrication process for a 1-transistor EEPROM memory device capable of low-voltage operation.

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27. Vo Hai H. (Gilroy CA), Flash EEPROM Memory system for low voltage operation and method.

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28. Chen Jian (San Jose CA) Radjy Nader (Palo Alto CA), Flash EEPROM array with floating substrate erase operation.

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29. Haddad Sameer S. (San Jose CA) Fang Hao (Cupertino CA), Flash EEPROM memory with improved discharge speed using substrate bias and method therefor.

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30. Tang Yuan (San Jose CA), Flash EEPROM memory with separate reference array.

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31. Sali Mauro,ITX ; Villa Corrado,ITX ; Carrera Marcello,ITX, Flash EEPROM with controlled discharge time of the word lines and source potentials after erase.

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32. Sali Mauro,ITX ; Villa Corrado,ITX ; Carrera Marcello,ITX, Flash EEPROM with controlled discharge time of the word lines and source potentials after erase.

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33. Dallabora Marco,ITX ; Villa Corrado,ITX ; Bettini Luigi,ITX, Flash EEPROM with on-chip erase source voltage generator.

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34. Marco Dallabora IT; Corrado Villa IT; Luigi Bettini IT, Flash EEPROM with on-chip erase source voltage generator.

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35. Ritu Shrivastava ; Chitranjan N. Reddy, Flash EPROM array with self-aligned source contacts and programmable sector erase architecture.

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36. Mihnea,Andrei; Chen,Chun, Flash memory.

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37. Park Eungjoon ; Pourkeramati Ali, Flash memory architecture and method of operation.

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38. Rinerson Darrell D. ; Lee Roger R. ; Chevallier Christophe J., Flash memory system having fast erase operation.

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39. Rinerson Darrell D. ; Lee Roger R. ; Chevallier Christophe J., Flash memory system having fast erase operation.

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40. Rinerson Darrell D. ; Lee Roger R. ; Chevallier Christophe J., Flash memory system having fast erase operation.

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41. Akaogi Takao (Kawasaki JPX) Kawashima Hiromi (Kawasaki JPX) Takeguchi Tetsuji (Kawasaki JPX) Hagiwara Ryoji (Kawasaki JPX) Kasa Yasushi (Kawasaki JPX) Itano Kiyoshi (Kawasaki JPX) Ogawa Yasushige (Ka, Flash memory with improved erasability and its circuitry.

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42. Akaogi Takao,JPX ; Ogawa Yasushige,JPX ; Kajita Tatsuya,JPX ; Watanabe Hisayoshi,JPX ; Yamashita Minoru,JPX, Flash-erasable semiconductor memory device having an improved reliability.

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43. Akaogi Takao,JPX ; Ogawa Yasushige,JPX ; Kajita Tatsuya,JPX ; Watanabe Hisayoshi,JPX ; Yamashita Minoru,JPX, Flash-erasable semiconductor memory device having an improved reliability.

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44. Akaogi Takao,JPX ; Ogawa Yasushige,JPX ; Kajita Tatsuya,JPX ; Watanabe Hisayoshi,JPX ; Yamashita Minoru,JPX, Flash-erasable semiconductor memory device having an improved reliability.

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45. Akaogi Takao,JPX ; Ogawa Yasushige,JPX ; Kajita Tatsuya,JPX ; Watanabe Hisayoshi,JPX ; Yamashita Minoru,JPX, Flash-erasable semiconductor memory device having an improved reliability.

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46. Akaogi Takao,JPX ; Ogawa Yasushige,JPX ; Kajita Tatsuya,JPX ; Watanabe Hisayoshi,JPX ; Yamashita Minoru,JPX, Flash-erasable semiconductor memory device having an improved reliability.

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47. Akaogi Takao,JPX ; Ogawa Yasushige,JPX ; Kajita Tatsuya,JPX ; Watanabe Hisayoshi,JPX ; Yamashita Minoru,JPX, Flash-erasable semiconductor memory device having improved reliability.

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48. Forbes, Leonard; Ahn, Kie Y., High density stepped, non-planar flash memory.

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49. Forbes, Leonard; Ahn, Kie Y., High density stepped, non-planar flash memory.

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50. Sethi Rakesh Balraj ; Norris Christopher S. ; Hu Genda J., High speed flash memory cell structure and method.

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51. Ghilardelli Andrea,ITX, High-voltage pump architecture for integrated electronic devices.

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52. Hsu, Kai-Chieh; Lee, Feng-Min; Lin, Yu-Yu, Iterative method and apparatus to program a programmable resistance memory element using stabilizing pulses.

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53. Ohtsuka Nobuaki, Level-shift circuit for driving word lines of negative gate erasable type flash memory.

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54. Yero Emilio Miguel,FRX, Load pump type of voltage generator circuit.

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55. Samachisa George (San Jose CA) Yuan Jack H. (Cupertino CA), Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors.

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56. Samachisa George (San Jose CA) Yuan Jack H. (Cupertino CA), Low voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectors.

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57. Hanneberg Armin,DEX ; Tempel Georg,DEX, MOS circuit configuration for switching high voltages on a semiconductor chip.

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58. Hung, Shuo-Nan; Lo, Chi; Hung, Chun-Hsiung, Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks.

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59. Lo, Chi; Hung, Shuo-Nan; Hung, Chun-Hsiung, Memory repair redundancy with array cache redundancy.

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60. Daga,Jean Michel, Method and apparatus for a dual power supply to embedded non-volatile memory.

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61. Hung, Shuo-Nan, Method and apparatus for copying data with a memory array having redundant memory.

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62. Engh Lawrence D. ; Herman Michael H., Method and apparatus for detecting the end of message recorded onto an array of memory elements.

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63. Jinbo Toshikatsu,JPX, Method and device for erasing non-volatile semiconductor memory with smaller erase variation.

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64. Jinbo Toshikatsu,JPX, Method and device for erasing non-volatile semiconductor memory with smaller erase variation.

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65. Baldi Livio,ITX ; Pio Federico,ITX, Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory de.

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66. Baldi Livio (Agrate Brianza ITX) Pio Federico (Milan ITX), Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory devi.

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67. Chaudhry,Samir; Roy,Pradip K., Method and structure for graded gate oxides on vertical and non-planar surfaces.

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68. Samachisa Gheorghe (San Jose CA) Fong Yupin K. (Fremont CA), Method and structure for programming floating gate memory cells.

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69. Toshikatsu Jinbo JP, Method for controlling a flash memory erase operation and flash memory erase operation controller.

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70. Campardo, Giovanni; Micheloni, Rino, Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices.

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71. Micheloni,Rino; Campardo,Giovanni, Method for erasing non-volatile memory cells and corresponding memory device.

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72. Brady, David Charles; Ma, Yi; Roy, Pradip Kumar, Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer.

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73. Keith R. Wald ; Chan-Sui Pang ; Yueh Yale Ma, Method for operating nonvolatile memory cells.

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74. Sali Mauro,ITX ; Dallabora Marco,ITX ; Carrera Marcello,ITX, Method for setting the threshold voltage of a reference memory cell.

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75. Berco, Danny, Method of erasing a flash EEPROM memory.

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76. Wang, Lee Z.; Huang, Jui-Hung, Method of erasing a flash EEPROM memory.

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77. Van Houdt Jan F.,BEX ; Haspeslagh Luc,BEX ; Deferm Ludo,BEX ; Groeseneken Guido,BEX ; Maes Herman,BEX, Method of erasing a flash EEPROM memory cell array optimized for low power consumption.

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78. Van Houdt Jan F.,BEX ; Haspeslagh Luc,BEX ; Deferm Ludo,BEX ; Groeseneken Guido,BEX ; Maes Herman,BEX, Method of erasing a flash EEPROM memory cell array optimized for low power consumption.

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79. Houdt Jan Van,BEX ; Wellekens Dirk,BEX, Method of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications.

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80. Janet S. Y. Wang ; Ravi S. Sunkavalli, Method of erasing a non-volatile memory cell using a substrate bias.

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81. Hara Hideki,JPX, Method of erasing data in nonvolatile semiconductor memory devices.

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82. Derhacobian Narbeth ; Van Buskirk Michael ; Sobeck Daniel ; Wang Janet S. Y. ; Chang Chi, Method of erasing non-volatile memory cells.

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83. Chen Jian (San Jose CA) Hsu James J. (Saratoga CA) Luan Shengwen (San Jose CA) Tang Yuan (San Jose CA) Liu David Kuan-Yu (Cupertino CA) Van Buskirk Michael A. (San Jose CA), Method of inhibiting degradation of ultra short channel charge-carrying devices during discharge.

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84. Ghneim Said N. ; Fulford ; Jr. H. Jim, Method of making non-volatile memory device having a floating gate with enhanced charge retention.

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85. Chi Chang ; Richard J. Huang ; Keizaburo Yoshie JP; Yu Sun, Method of making tungsten gate MOS transistor and memory cell by encapsulating.

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86. Arthur Arthur Wang ; Jein-Chen Young ; Ming-Sang Kwan, Method of operating flash memory.

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87. Van Houdt Jan F.,BEX ; Haspeslagh Luc,BEX ; Deferm Ludo,BEX ; Groeseneken Guido,BEX ; Maes Herman,BEX, Method of programming a flash EEPROM memory cell array optimized for low power consumption.

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88. Cleveland Lee, Method to provide a reduced constant E-field during erase of EEPROMs for reliability improvement.

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89. Mihnea,Andrei; Chen,Chun, Methods for erasing flash memory.

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90. Mihnea,Andrei; Chen,Chun, Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices.

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91. Van Houdt Jan,BEX ; Wellekens Dirk,BEX, Methods of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications.

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92. Van Houdt Jan,BEX ; Wellekens Dirk,BEX, Methods of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications.

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93. Kim, Jin-Woo, Methods of operating semiconductor memory devices having split gate-type non-volatile memory cells.

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94. Jin-Woo Kim KR, Methods of operating split-gate type non-volatile memory cells.

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95. Sali Mauro (S. Angelo Lodigiano ITX) Villa Corrado (Sovico ITX) Carrera Marcello (Trescore Balneario ITX), Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices.

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96. Sali Mauro,ITX ; Villa Corrado,ITX ; Carrera Marcello,ITX, Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices.

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97. Lee Hsiao-Lun ; Park Eung Joon ; Pourkeramati Ali, Non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions.

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98. Ghneim Said N. ; Fulford ; Jr. H. Jim, Non-volatile memory device having a floating gate with enhanced charge retention.

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99. Chi Chang ; Richard J. Huang ; Keizaburo Yoshie JP; Yu Sun, Non-volatile memory device with encapsulated tungsten gate and method of making same.

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100. Roy, Kumar Pradip; Singh, Ranbir, Non-volatile memory semiconductor device including a graded, grown, high quality control gate oxide layer and associated methods.

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101. Roy, Kumar Pradip; Singh, Ranbir, Non-volatile memory semiconductor device including a graded, grown, high quality oxide layer and associated methods.

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102. Chevallier,Christophe J., Non-volatile memory with test rows for disturb detection.

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103. Iwahashi Hiroshi,JPX, Non-volatile semiconductor memory device.

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104. Hiroshi Iwahashi JP, Non-volatile semiconductor memory device and data programming method.

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105. Hiroshi Iwahashi JP, Non-volatile semiconductor memory device and data programming method.

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106. Iwahashi Hiroshi,JPX, Non-volatile semiconductor memory device and data programming method.

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107. Iwahashi Hiroshi,JPX, Non-volatile semiconductor memory device and data programming method.

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108. Iwahashi, Hiroshi, Non-volatile semiconductor memory device and data programming method.

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109. Iwahashi, Hiroshi, Non-volatile semiconductor memory device and data programming method.

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110. Iwahashi,Hiroshi, Non-volatile semiconductor memory device and data programming method.

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111. Iwahashi,Hiroshi, Non-volatile semiconductor memory device and data programming method.

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112. Tanaka Tomoharu,JPX ; Momodomi Masaki,JPX ; Kato Hideo,JPX ; Nakai Hiroto,JPX ; Tanaka Yoshiyuki,JPX ; Shirota Riichiro,JPX ; Aritome Seiichi,JPX ; Itoh Yasuo,JPX ; Iwata Yoshihisa,JPX ; Nakamura Hir, Non-volatile semiconductor memory device and memory system using the same.

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113. Tanaka Tomoharu,JPX ; Momodomi Masaki,JPX ; Kato Hideo,JPX ; Nakai Hiroto,JPX ; Tanaka Yoshiyuki,JPX ; Shirota Riichiro,JPX ; Aritome Seiichi,JPX ; Itoh Yasuo,JPX ; Iwata Yoshihisa,JPX ; Nakamura Hir, Non-volatile semiconductor memory device and memory system using the same.

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114. Tanaka Tomoharu,JPX ; Momodomi Masaki,JPX ; Kato Hideo,JPX ; Nakai Hiroto,JPX ; Tanaka Yoshiyuki,JPX ; Shirota Riichiro,JPX ; Aritome Seiichi,JPX ; Itoh Yasuo,JPX ; Iwata Yoshihisa,JPX ; Nakamura Hir, Non-volatile semiconductor memory device and memory system using the same.

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115. Tanaka, Tomoharu; Momodomi, Masaki; Kato, Hideo; Nakai, Hiroto; Tanaka, Yoshiyuki; Shirota, Riichiro; Aritome, Seiichi; Itoh, Yasuo; Iwata, Yoshihisa; Nakamura, Hiroshi; Odaira, Hideko; Okamoto, Yuta, Non-volatile semiconductor memory device and memory system using the same.

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116. Tanaka, Tomoharu; Momodomi, Masaki; Kato, Hideo; Nakai, Hiroto; Tanaka, Yoshiyuki; Shirota, Riichiro; Aritome, Seiichi; Itoh, Yasuo; Iwata, Yoshihisa; Nakamura, Hiroshi; Odaira, Hideko; Okamoto, Yuta, Non-volatile semiconductor memory device and memory system using the same.

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117. Tanaka,Tomoharu; Momodomi,Masaki; Kato,Hideo; Nakai,Hiroto; Tanaka,Yoshiyuki; Shirota,Riichiro; Aritome,Seiichi; Itoh,Yasuo; Iwata,Yoshihisa; Nakamura,Hiroshi; Odaira,Hideko; Okamoto,Yutaka; Asano,Ma, Non-volatile semiconductor memory device and memory system using the same.

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118. Sekiguchi Mitsuru,JPX, Non-volatile semiconductor memory device having trapped charges pulled out.

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119. Iwahashi Hiroshi,JPX, Non-volatile semiconductor memory device with a plurality of programming voltage levels.

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120. Tanaka Tomoharu,JPX ; Momodomi Masaki,JPX ; Kato Hideo,JPX ; Nakai Hiroto,JPX ; Tanaka Yoshiyuki,JPX ; Shirota Riichiro,JPX ; Aritome Seiichi,JPX ; Itoh Yasuo,JPX ; Iwata Yoshihisa,JPX ; Nakamura Hir, Non-volatile semiconductor memory device with an improved verify voltage generator.

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121. Iwahashi, Hiroshi, Non-volatile semiconductor memory device with programming voltage generating system and data programming method.

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122. Wong Ting-wah, Nonvolatile memory.

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123. Sakamoto,Yoshinori; Bando,Tatsuya, Nonvolatile memory and method of erasing for nonvolatile memory.

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124. Sakamoto,Yoshinori; Bando,Tatsuya, Nonvolatile memory and method of erasing for nonvolatile memory.

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125. Seki,Koichi; Wada,Takeshi; Muto,Tadashi; Shoji,Kazuyoshi; Kubota,Yasurou; Kume,Hitoshi, Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory.

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126. Wong Ting-wah, Nonvolatile memory capable of using substrate hot electron injection.

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127. Fastow, Richard M.; Chang, Chi; Derhacobian, Narbeh, Nonvolatile memory cell with a nitridated oxide layer.

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128. Seki, Koichi; Wada, Takeshi; Muto, Tadashi; Shoji, Kazuyoshi; Kubota, Yasurou; Kume, Hitoshi, Nonvolatile semiconductor memory apparatus.

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129. Atsumi Shigeru,JPX ; Banba Hironori,JPX, Nonvolatile semiconductor memory device.

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130. Atsumi Shigeru,JPX ; Banba Hironori,JPX, Nonvolatile semiconductor memory device.

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131. Atsumi Shigeru,JPX ; Banba Hironori,JPX, Nonvolatile semiconductor memory device.

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132. Atsumi Shigeru,JPX ; Tanaka Sumio,JPX, Nonvolatile semiconductor memory device.

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133. Atsumi Shigeru,JPX ; Tanaka Sumio,JPX, Nonvolatile semiconductor memory device.

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134. Atsumi, Shigeru; Banba, Hironori, Nonvolatile semiconductor memory device.

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135. Koichi Seki JP; Takeshi Wada JP; Tadashi Muto JP; Kazuyoshi Shoji JP; Yasurou Kubota JP; Hitoshi Kume JP, Nonvolatile semiconductor memory device.

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136. Seki Koichi,JPX ; Wada Takeshi,JPX ; Muto Tadashi,JPX ; Shoji Kazuyoshi,JPX ; Kubota Yasurou,JPX ; Kume Hitoshi,JPX, Nonvolatile semiconductor memory device.

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137. Seki Koichi,JPX ; Wada Takeshi,JPX ; Muto Tadashi,JPX ; Shoji Kazuyoshi,JPX ; Kubota Yasurou,JPX ; Kume Hitoshi,JPX, Nonvolatile semiconductor memory device.

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138. Seki Koichi,JPX ; Wada Takeshi,JPX ; Muto Tadashi,JPX ; Shoji Kazuyoshi,JPX ; Kubota Yasurou,JPX ; Kume Hitoshi,JPX, Nonvolatile semiconductor memory device.

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139. Seki Koichi,JPX ; Wada Takeshi,JPX ; Muto Tadashi,JPX ; Shoji Kazuyoshi,JPX ; Kubota Yasurou,JPX ; Kume Hitoshi,JPX, Nonvolatile semiconductor memory device.

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140. Seki Koichi,JPX ; Wada Takeshi,JPX ; Muto Tadashi,JPX ; Shoji Kazuyoshi,JPX ; Kubota Yasurou,JPX ; Kume Hitoshi,JPX, Nonvolatile semiconductor memory device.

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141. Seki Koichi,JPX ; Wada Takeshi,JPX ; Muto Tadashi,JPX ; Shoji Kazuyoshi,JPX ; Kubota Yasurou,JPX ; Kume Hitoshi,JPX, Nonvolatile semiconductor memory device.

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142. Seki Koichi,JPX ; Wada Takeshi,JPX ; Muto Tadashi,JPX ; Shoji Kazuyoshi,JPX ; Kubota Yasurou,JPX ; Kume Hitoshi,JPX, Nonvolatile semiconductor memory device.

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143. Seki, Koichi; Wada, Takeshi; Muto, Tadashi; Shoji, Kazuyoshi; Kubota, Yasurou; Kume, Hitoshi, Nonvolatile semiconductor memory device.

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144. Seki,Koichi; Wada,Takeshi; Muto,Tadashi; Shoji,Kazuyoshi; Kubota,Yasurou; Kume,Hitoshi, Nonvolatile semiconductor memory device.

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145. Seki,Koichi; Wada,Takeshi; Muto,Tadashi; Shoji,Kazuyoshi; Kubota,Yasurou; Kume,Hitoshi, Nonvolatile semiconductor memory device.

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146. Shigeru Atsumi JP; Hironori Banba JP, Nonvolatile semiconductor memory device.

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147. Atsumi Shigeru (Tokyo JPX) Tanaka Sumio (Tokyo JPX), Nonvolatile semiconductor memory device having a word line to which a negative voltage is applied.

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148. Atsumi Shigeru,JPX ; Tanaka Sumio,JPX, Nonvolatile semiconductor memory device having row decoder.

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149. Atsumi Shigeru,JPX ; Tanaka Sumio,JPX, Nonvolatile semiconductor memory device having row decoder.

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150. Atsumi Shigeru,JPX ; Tanaka Sumio,JPX, Nonvolatile semiconductor memory device having row decoder.

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151. Atsumi Shigeru (Tokyo JPX) Tanaka Sumio (Tokyo JPX), Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erase mod.

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152. Atsumi Shigeru,JPX ; Tanaka Sumio,JPX, Nonvolatile semiconductor memory device having row decoder supplying a negative potential to wordlines during erase mod.

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153. Atsumi Shigeru,JPX ; Tanaka Sumio,JPX, Nonvolatile semiconductor memory device including a circuit for providing a boosted potential.

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154. Atsumi, Shigeru; Tanaka, Sumio, Nonvolatile semiconductor memory device including a circuit for providing a boosted potential.

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155. Atsumi Shigeru,JPX ; Tanaka Sumio,JPX, Nonvolatile semiconductor memory device including potential generating circuit.

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156. Brigati Alessandro,FRX ; Demange Nicolas,FRX ; Aulas Maxence,FRX ; Guedj Marc,FRX, Phase generator circuit for charge pump type or negative supply circuit.

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157. Tomita Naoto,JPX, Power source circuit device used for a semiconductor memory.

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158. Salter, III, Robert M.; Han, Kyung Joon; Kim, Sung Rae; Chan, Nigel, Programming method for non-volatile memory and non-volatile memory-based programmable logic device.

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159. Lin, Yu-Yu; Lee, Feng-Min, ReRAM array configuration for bipolar operation.

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160. Lin Yu-Shen,TWX ; Shiau Tzeng-Huei,TWX ; Wan Ray-Lin, Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices.

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161. Campardo Giovanni,ITX ; Micheloni Rino,ITX, Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector.

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162. Chevallier Christophe J. ; Lakhani Vinod C., Segmented non-volatile memory array with multiple sources with improved word line control circuitry.

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163. Richard M. Fastow ; Mark W. Randolph ; Shane C. Hollmer, Select transistor architecture for a virtual ground non-volatile memory cell array.

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164. Timothy J. Thurgate ; Daniel Sobek, Selective erasure of a non-volatile memory cell of a flash memory device.

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165. Saito Hidetoshi,JPX ; Kuriyama Masao,JPX ; Honda Yasuhiko,JPX ; Kato Hideo,JPX, Semiconductor memory and nonvolatile semiconductor memory having redundant circuitry for replacing defective memory cell.

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166. Saito, Hidetoshi; Kuriyama, Masao; Honda, Yasuhiko; Kato, Hideo, Semiconductor memory device having redundant circuitry for replacing defective memory cell.

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167. Nakagome Yoshinobu (Hachioji JPX) Itoh Kiyoo (Higashikurume JPX) Tanaka Hitoshi (Tachikawa JPX) Watanabe Yasushi (Hanno JPX) Kume Eiji (Matsuyama JPX) Isoda Masanori (Sayama JPX) Yamasaki Eiji (Fussa, Semiconductor memory operating with low supply voltage.

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168. Wang Arthur ; Young Jein-Chen ; Kwan Ming, Semiconductor structure for flash memory enabling low operating potentials.

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169. Fastow, Richard M.; Hollmer, Shane C.; Chen, Pau-Ling; Van Buskirk, Michael; Higashitani, Masaaki, Sidewall NROM and method of manufacture thereof for non-volatile memory cells.

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170. Hung, Chih-Wei; Sung, Da, Structure, fabrication method and operating method for flash memory.

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171. Hung, Chih-Wei; Sung, Da, Structure, fabrication method and operating method for flash memory.

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172. Sunkavalli Ravi S., Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell.

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173. Frayer Jack E. (Boulder Creek CA) Lattanzi John D. (Palo Alto CA) Tsao Shouchang (Sunnyvale CA) Pang Chan-Sui (Sunnyvale CA) Ma Yueh Y. (Los Altos Hills CA), Switch driver circuit for providing small sector sizes for negative gate erase flash EEPROMS using a standard twin-well.

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174. Chen, Yuanning; Chetlur, Sundar Srinivasan; Roy, Pradip Kumar, TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIE.

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175. Park,Jongmin, Technique for programming floating-gate transistor used in circuitry as flash EPROM.

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176. Okhonin, Serguei; Nagoga, Mikhail; Bassin, Cedric, Techniques for reading a memory cell with electrically floating body transistor.

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177. Ken Kawai JP, Test circuit for semiconductor IC device.

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178. Liu Yowjuang W. ; Sun Yu, Three-dimensional complementary field effect transistor process and structures.

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179. Liu Yowjuang W. ; Haddad Sameer S., Three-dimensional non-volatile memory.

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180. Liu Yowjuang W. ; Haddad Sameer S., Three-dimensional non-volatile memory.

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181. Shokouhi, Farshid; Sheen, Ben Y.; Lin, Qi, Tunable circuit for detection of negative voltages.

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182. Narbeh Derhacobian ; Michael Van Buskirk ; Chi Chang ; Daniel Sobek, Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure.

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183. Derhacobian, Narbeh; Van Buskirk, Michael; Chang, Chi; Sobek, Daniel, Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure.

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184. Derhacobian, Narbeh; Sobek, Daniel, Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure.

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185. Narbeh Derhacobian ; Michael Van Buskirk ; Chi Chang ; Daniel Sobek, Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure.

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186. Lin, Yu-Yu; Lee, Feng-Min, Verify scheme for ReRAM.

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187. Chen Chun, Voltage regulation for integrated circuit memory.

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