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Method for operating a multiple page programmable logic device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0636592 (1991-01-02)
발명자 / 주소
  • Pickett Scott K. (San Jose CA) Luich Thomas M. (Campbell CA) Swift
  • IV Arthur L. (Welches OR)
출원인 / 주소
  • National Semiconductor Corp. (Santa Clara CA 02)
인용정보 피인용 횟수 : 92  인용 특허 : 0

초록 ▼

A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said page

대표청구항 ▼

A method for operating a logic array circuit comprising: a plurality of L input leads for receiving a plurality of input signals, where L is a first positive integer; a set of N first logic arrays, where N is a second positive integer greater than or equal to one, each of said N first logic arrays i

이 특허를 인용한 특허 (92)

  1. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
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  2. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
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  3. Schuyler E. Shimanek, Complex programmable logic device with lookup table.
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  4. Shimanek Schuyler E. ; Davies Thomas J., Condensed single block PLA plus.
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  5. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
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  6. Scalera Stephen M. ; Vazquez Jose R., Context switchable field programmable gate array with public-private addressable sharing of intermediate data.
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  7. DeHon Andre ; Bolotski Michael ; Knight ; Jr. Thomas F., DPGA-coupled microprocessors.
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  8. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  9. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  10. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  11. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
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  12. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
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  13. Vorbach, Martin, Data processing system.
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  14. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
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  15. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
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  16. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.
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  17. Lin, Guu; Tran, Stephanie; Pederson, Bruce; Vest, Brad; Park, Jim; Schleicher, Jay, Flexible macrocell interconnect.
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  18. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
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  19. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.
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  20. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
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  21. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
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  22. Vorbach Martin,DEX ; Munch Robert,DEX, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
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  23. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
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  24. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
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  25. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  26. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  27. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  28. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  29. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  30. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
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  31. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  32. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  33. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  34. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  35. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  38. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
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  39. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
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  40. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
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  41. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  42. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
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  43. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
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  44. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
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  45. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
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  46. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  47. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
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  48. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
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  49. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  50. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  54. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
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  56. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
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  57. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.
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