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Electrically programmable non-volatile memory device and manufacturing method thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/68
  • H01L-027/10
  • H01L-029/34
출원번호 US-0630439 (1990-12-20)
우선권정보 JP-0161813 (1988-06-28)
발명자 / 주소
  • Arima Hideaki (Hyogo JPX) Okumura Yoshinori (Hyogo JPX) Genjo Hideki (Hyogo JPX) Ogoh Ikuo (Hyogo JPX) Yuzuriha Kohjiroh (Hyogo JPX) Nakashima Yuichi (Hyogo JPX)
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha (Tokyo JPX 03)
인용정보 피인용 횟수 : 50  인용 특허 : 0

초록 ▼

A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating la

대표청구항 ▼

In a semiconductor memory device having a semiconductor substrate of a first conductivity type with a major surface and a plurality of memory cells formed spaced apart and separated from one another by an isolation layer formed on said major surface, each of said memory cells comprising: first and s

이 특허를 인용한 특허 (50)

  1. Wang, Chih Hsin, Array of floating gate memory cells having strap regions and a peripheral logic device region.
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  2. Hong Gary (Hsin-Chu TWX), Flash EEPROM memory cell with polysilicon source/drain.
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  3. Wang, Chih Hsin; Levi, Amitay, Method of forming a semiconductor array of floating gate memory cells and strap regions.
    상세보기
  4. Wang, Chih Hsin, Method of forming a semiconductor array of floating gate memory cells and strap regions, and a memory array and strap regions made thereby.
    상세보기
  5. Wang, Chih Hsin, Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region.
    상세보기
  6. Chern,Geeng Chuan; Levi,Amitay; Lee,Dana, Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric.
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  7. Klinger, Pavel; Levi, Amitay, Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates.
    상세보기
  8. Chang Kuang-Yeh (Los Gatos CA) Nariani Subhash R. (San Jose CA) Boardman William J. (San Jose CA), Method of making flash memory cell.
    상세보기
  9. Ghneim Said N. ; Fulford ; Jr. H. Jim, Method of making non-volatile memory device having a floating gate with enhanced charge retention.
    상세보기
  10. Wang, Chih Hsin; Yeh, Bing, Method of operating a semiconductor memory array of floating gate memory cells with horizontally oriented edges.
    상세보기
  11. Yeh, Bing; Kianian, Sohrab; Hu, Yaw Wen, Method of programming electrons onto a floating gate of a non-volatile memory cell.
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  12. Do, Nhan; Levi, Amitay, Non-volatile memory cell with self aligned floating and erase gates, and method of making same.
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  13. Ghneim Said N. ; Fulford ; Jr. H. Jim, Non-volatile memory device having a floating gate with enhanced charge retention.
    상세보기
  14. Yu Shih-Chiang, Non-volatile semiconductor memory cell with control gate and floating gate and select gate located above the channel.
    상세보기
  15. Chern, Geeng-Chuan Michael; Su, Chien-Sheng, Self aligned method of forming a semiconductor array of non-volatile memory cells.
    상세보기
  16. Kianian,Sohrab; Wang,Chih Hsin, Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line.
    상세보기
  17. Kianian,Sohrab, Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby.
    상세보기
  18. Kianian,Sohrab, Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby.
    상세보기
  19. Kianian,Sohrab; Wang,Chih Hsin, Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor.
    상세보기
  20. Chen,Bomy; Tsui,Ying Kit; Lu,Wen Juei, Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region.
    상세보기
  21. Wang, Chih Hsin, Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate protruding portions.
    상세보기
  22. Wang,Chih Hsin, Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers.
    상세보기
  23. Chern, Geeng-Chuan, Self aligned method of forming a semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges, and a memory array made thereby.
    상세보기
  24. Klinger, Pavel; Maheshwarla, Sreeni, Self aligned method of forming non-volatile memory cells with flat word line.
    상세보기
  25. Wang, Chih Hsin, Self-aligned floating gate poly for a flash E2PROM cell.
    상세보기
  26. Chen, Bomy; Lee, Dana, Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby.
    상세보기
  27. Hu, Yaw Wen; Kianian, Sohrab, Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate.
    상세보기
  28. Kotov, Alexander; Levi, Amitay; Nguyen, Hung Q.; Klinger, Pavel, Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby.
    상세보기
  29. Johnson, Jeffrey B.; Lam, Chung H.; Lee, Dana; Martin, Dale W.; Rankin, Jed H., Self-aligned non-volatile random access memory cell and process to make the same.
    상세보기
  30. Wang, Chih Hsin; Levi, Amitay, Semiconductor array of floating gate memory cells and strap regions.
    상세보기
  31. Shimamoto, Hiromi; Uchino, Takashi; Shiba, Takeo; Ohnishi, Kazuhiro; Tamaki, Yoichi; Kobayashi, Takashi; Kikuchi, Toshiyuki; Ikeda, Takahide, Semiconductor device and process of producing the same.
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  32. Shimamoto,Hiromi; Uchino,Takashi; Shiba,Takeo; Ohnishi,Kazuhiro; Tamaki,Yoichi; Kobayashi,Takashi; Kikuchi,Toshiyuki; Ikeda,Takahide, Semiconductor device and process of producing the same.
    상세보기
  33. Bolotnikov, Alexander Viktorovich; Losee, Peter Almern, Semiconductor devices having channel regions with non-uniform edge.
    상세보기
  34. Kianian, Sohrab; Wang, Chih Hsin, Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line.
    상세보기
  35. Kianian, Sohrab; Wang, Chih Hsin, Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor.
    상세보기
  36. Chen, Bomy; Lee, Dana; Tran, Hieu Van, Semiconductor memory array of floating gate memory cells with buried floating gate.
    상세보기
  37. Chen,Bomy; Lee,Dana, Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region.
    상세보기
  38. Hu, Yaw Wen; Kianian, Sohrab, Semiconductor memory array of floating gate memory cells with buried source line and floating gate.
    상세보기
  39. Chen, Bomy; Tsui, Ying Kit; Lu, Wen-Juei, Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region.
    상세보기
  40. Wang, Chih Hsin, Semiconductor memory array of floating gate memory cells with control gate spacer portions.
    상세보기
  41. Wang, Chih Hsin, Semiconductor memory array of floating gate memory cells with control gates protruding portions.
    상세보기
  42. Chern, Geeng-Chuan, Semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges.
    상세보기
  43. Wang, Chih Hsin; Yeh, Bing, Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges.
    상세보기
  44. Wang, Chih Hsin; Levi, Amitay, Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling.
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  45. Wang, Chih Hsin; Levi, Amitay, Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling.
    상세보기
  46. Klinger, Pavel; Levi, Amitay, Semiconductor memory array of floating gate memory cells with program/erase and select gates.
    상세보기
  47. Klinger,Pavel; Levi,Amitay, Semiconductor memory array of floating gate memory cells with program/erase and select gates.
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  48. Chern, Geeng-Chuan, Semiconductor memory array of floating gate memory cells with vertical control gate sidewalls and insulation spacers.
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  49. Kito Takayuki,JPX, Vertical double diffused MOSFET and method for manufacturing same.
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  50. Takayuki Kito JP, Vertical double diffused MOSFET and method for manufacturing same.
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