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SOI/semiconductor heterostructure fabrication by wafer bonding of polysilicon to titanium 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
  • H01L-021/76
출원번호 US-0633647 (1990-12-20)
발명자 / 주소
  • Moslehi Mehrdad M. (Dallas TX)
출원인 / 주소
  • Texas Instruments Incorporated (Dallas TX 02)
인용정보 피인용 횟수 : 65  인용 특허 : 0

초록

This is a method of forming a semiconductor-on-insulator wafer from two individual wafers. The method comprises: forming a layer of metal (e.g. titanium 24) on a first wafer; forming an insulator (e.g. oxide 32) on a second wafer; forming a bonding layer (e.g. poly 38) over the insulator; anisotropi

대표청구항

A method of forming a semiconductor-on-insulator wafer from two individual wafers; said method comprising: a. forming a layer of metal on a first wafer; b. forming an insulator on a second wafer; c. forming a bonding layer over said insulator; d. anisotropically etching said bonding layer to form ch

이 특허를 인용한 특허 (65)

  1. Cha Gi-ho,KRX ; Lee Byoung-hun,KRX, Apparatus and methods for wafer debonding using a liquid jet.
  2. Cha Gi-ho,KRX ; Lee Byoung-hun,KRX, Apparatus and methods for wafer debonding using a liquid jet.
  3. Farooq, Mukta G.; Li, Zhengwen; Luo, Zhijiong; Zhu, Huilong, Bonded structure employing metal semiconductor alloy bonding.
  4. Farooq, Mukta G.; Li, Zhengwen; Luo, Zhijiong; Zhu, Huilong, Bonded structure employing metal semiconductor alloy bonding.
  5. Linn Jack H. ; Lowry Robert K. ; Rouse George V. ; Buller James F., Bonded wafer processing with oxidative bonding.
  6. Linn, Jack H.; Lowry, Robert K.; Rouse, George V.; Buller, James F., Bonded wafer with metal silicidation.
  7. Zahurak, John K.; Tang, Sanh D.; Heineck, Lars P.; Roberts, Martin C.; Mueller, Wolfgang; Liu, Haitao, Circuit structures, memory circuitry, and methods.
  8. Francois J. Henley ; Michael A. Brayan ; William G. En, Cleaving process to fabricate multilayered substrates using low implantation doses.
  9. Henley,Francois J.; Bryan,Michael A.; En,William G., Cleaving process to fabricate multilayered substrates using low implantation doses.
  10. Francois J. Henley ; Nathan Cheung, Controlled cleavage process and device for patterned films.
  11. Henley, Francois J.; Cheung, Nathan, Controlled cleavage process and device for patterned films.
  12. Francois J. Henley ; Nathan W. Cheung, Controlled cleavage process and resulting device using beta annealing.
  13. Henley, Francois J.; Cheung, Nathan, Controlled cleavage process using pressurized fluid.
  14. Henley,Francois J.; Cheung,Nathan W., Controlled cleaving process.
  15. Henley,Francois J.; Cheung,Nathan W., Controlled cleaving process.
  16. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  17. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  18. Henley, Francois J.; Cheung, Nathan W., Controlled process and resulting device.
  19. Henley,Francois J.; Cheung,Nathan W., Controlled process and resulting device.
  20. Qin, Shu; Zhang, Ming, Devices, systems and methods for electrostatic force enhanced semiconductor bonding.
  21. Kitch, Vassili, Fabrication of copper-containing region such as electrical interconnect.
  22. Tang, Sanh D.; Zahurak, John K.; Juengling, Werner, Floating body cell structures, devices including same, and methods for forming same.
  23. Tang, Sanh D.; Zahurak, John K.; Juengling, Werner, Floating body cell structures, devices including same, and methods for forming same.
  24. Tang, Sanh D.; Zahurak, John K.; Juengling, Werner, Floating body cell structures, devices including same, and methods for forming same.
  25. Tang, Sanh D.; Zahurak, John K.; Juengling, Werner, Floating body cell structures, devices including same, and methods for forming same.
  26. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  27. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  28. Henley, Francois J., Layer transfer of films utilizing controlled propagation.
  29. Henley, Francois J., Layer transfer of films utilizing controlled shear region.
  30. Tang, Sanh D., Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.
  31. Tang, Sanh D., Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.
  32. Ohmi, Kazuaki; Yonehara, Takao; Sakaguchi, Kiyofumi; Yanagita, Kazutaka, Method and apparatus for separating composite member using fluid.
  33. Francois J. Henley ; Nathan W. Cheung, Method and device for controlled cleaving process.
  34. Henley, Francois J.; Cheung, Nathan W., Method and device for controlled cleaving process.
  35. Henley,Francois J.; Cheung,Nathan, Method and device for controlled cleaving process.
  36. Henley, Francois J., Method and structure for fabricating solar cells using a thick layer transfer process.
  37. Lesk Israel A. (Phoenix AZ) Robb Francine Y. (Tempe AZ) Terry Lewis E. (Phoenix AZ) Secco d\Aragona Frank (Scottsdale AZ), Method of forming a conductive diffusion barrier.
  38. Morrow, Patrick; List, R. Scott; Kim, Sarah E., Methods of forming backside connections on a wafer stack.
  39. Morrow,Patrick; List,R. Scott; Kim,Sarah E., Methods of forming backside connections on a wafer stack.
  40. Malik, Igor J.; Kang, Sien G.; Fuerfanger, Martin; Kirk, Harry; Flat, Ariel; Current, Michael Ira; Ong, Philip James, Non-contact etch annealing of strained layers.
  41. Bryan, Michael A.; Kai, James K., Nozzle for cleaving substrates.
  42. Bryan, Michael A., Particle distribution method and resulting structure for a layer transfer process.
  43. Buynoski Matthew, Practical way to remove heat from SOI devices.
  44. Henley, Francois J.; Brailove, Adam, Race track configuration and method for wafering silicon solar substrates.
  45. Ohmi Tadahiro,JPX ; Tanaka Nobuyoshi,JPX ; Ushiki Takeo,JPX ; Shinohara Toshikuni,JPX ; Nitta Takahisa,JPX, SOI bonding structure.
  46. Ni, Chyi-Tsong; Wang, I-Shi; Lee, Hsin-Kuei; Su, Ching-Hou, Semiconductor apparatus.
  47. Ni, Chyi-Tsong; Wang, I-Shi; Lee, Hsin-Kuei; Su, Ching-Hou, Semiconductor apparatus including a metal alloy between a first contact and a second contact.
  48. Tang, Sanh D.; Zahurak, John K., Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same.
  49. Tang, Sanh D.; Zahurak, John K., Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same.
  50. Tang, Sanh D.; Zahurak, John K., Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same.
  51. Tang, Sanh D.; Zahurak, John K., Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same.
  52. Tang, Sanh D.; Zhang, Ming, Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices.
  53. Tang, Sanh D.; Zhang, Ming, Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices.
  54. Sinha, Nishant; Sandhu, Gurtej S.; Smythe, John, Semiconductor material manufacture.
  55. Tang, Sanh D.; Zhang, Ming; Bayless, Andrew M.; Zahurak, John K., Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures.
  56. Henley, Francois J.; Cheung, Nathan W., Silicon-on-silicon hybrid wafer assembly.
  57. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  58. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  59. Henley, Francois; Lamm, Al; Chow, Yi-Lei, Substrate cleaving under controlled stress conditions.
  60. Brailove, Adam; Liu, Zuqin; Henley, Francois J.; Lamm, Albert J., Techniques for forming thin films by implantation with reduced channeling.
  61. Tang, Sanh D., Thyristor based memory cells, devices and systems including the same and methods for forming the same.
  62. Tang, Sanh D., Thyristor-based memory cells, devices and systems including the same and methods for forming the same.
  63. Tang, Sanh D., Thyristor-based memory cells, devices and systems including the same and methods for forming the same.
  64. Nemati, Farid; Robins, Scott T.; Gupta, Rajesh N., Thyristors.
  65. Nemati, Farid; Robins, Scott T.; Gupta, Rajesh N., Thyristors, methods of programming thyristors, and methods of forming thyristors.
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