IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
US-0705840
(1991-05-28)
|
|
발명자
/ 주소 |
- Lee Chong U. (San Diego CA)
|
| 출원인 / 주소 |
- Qualcomm Incorporated (02)
|
| 인용정보 |
피인용 횟수 :
206 인용 특허 :
0 |
초록
▼
An image compression system and method for compressing image data for transmission. Each block and corresponding sub-blocks of pixel data is subjected to a discrete cosine transform (DCT) operation. Varying levels of sub-blocks of resulting corresponding transform coefficients are selected for const
An image compression system and method for compressing image data for transmission. Each block and corresponding sub-blocks of pixel data is subjected to a discrete cosine transform (DCT) operation. Varying levels of sub-blocks of resulting corresponding transform coefficients are selected for construction into a composite transform coefficient block corresponding to each input block of pixel data. The selection of transform coefficient block size for the composite block is determined by a comparison process between transform block and sub-block coding efficiency. The composite block is variable length coded to further reduce bit count in the compressed data.
대표청구항
▼
An image compression system for compressing a 16×16 block of pixel data comprising: first transform means for receiving and performing 2×2 discrete cosine transform (DCT) operations on said block of pixel data, and providing a corresponding block of sixty-four 2×2 DCT coefficient value sub-blocks; s
An image compression system for compressing a 16×16 block of pixel data comprising: first transform means for receiving and performing 2×2 discrete cosine transform (DCT) operations on said block of pixel data, and providing a corresponding block of sixty-four 2×2 DCT coefficient value sub-blocks; second transform means for receiving and performing 4×4 DCT operations on said block of pixel data, and providing a corresponding block of sixteen 4×4 DCT coefficient value sub-blocks; third transform means for receiving and performing 8×8 DCT operations on said block of pixel data, and providing a corresponding block of four 8×8 DCT coefficient value sub-blocks; fourth transform means for receiving and performing a 16×16 DCT operation on said block of pixel data, and providing a corresponding 16×16 DCT coefficient value block; first memory means for storing bit values each corresponding to a number of bits required to encode according to a predetermined encoding format each different 2×2 DCT coefficient value, said first memory means for receiving each 2×2 DCT coefficient value sub-block and providing a corresponding first set of bit values; second memory means for storing bit values each corresponding to a number of bits required to encode according to a predetermined encoding format each different 4×4 DCT coefficient value, said second memory means for receiving each 4×4 DCT coefficient value sub-block and providing a corresponding second set of bit values; third memory means for storing bit values each corresponding to a number of bits required to encode according to a predetermined encoding format each different 8×8 DCT coefficient value, said third memory means for receiving each 8×8 DCT coefficient value sub-blocks and providing a corresponding third set of bit values; fourth memory means for storing bit values each corresponding to a number of bits required to encode according to a predetermined encoding format each different 16×16 DCT coefficient value, said fourth memory means for receiving said 16×16 DCT coefficient value block and providing a corresponding fourth set of bit values; first code length summer means for, receiving said first set of bit values, summing ones of said first set of bit values corresponding to each respective 2×2 DCT coefficient value sub-block and providing corresponding first code length sum values; second code length summer means for, receiving said second set of bit values, summing ones of said second set of bit values corresponding to each respective 4×4 DCT coefficient value sub-block and providing corresponding second code length sum values; third code length summer means for, receiving said third set of bit values, summing ones of said third set of bit values corresponding to each respective 8×8 DCT coefficient value sub-block and providing corresponding third code length sum values; fourth code length summer means for, receiving said fourth set of bit values, summing said fourth set of bit values and providing a corresponding fourth code length sum value; first adder means for receiving and adding predetermined groups of said first code length sum values, and providing corresponding first adder values; first comparator means for receiving and comparing each first adder value with a predetermined corresponding second code length sum value, and providing a corresponding first comparison value; first multiplexer means for receiving each first adder value, each corresponding second code length sum value, and each corresponding first comparison value and for providing a first multiplexer value selected from one of each first adder value and corresponding second code length sum value in accordance with said first comparison value; first register means for receiving and storing in a predetermined order each first comparison value; second adder means for receiving and adding predetermined groups of first multiplexer values, and providing corresponding second adder values; second comparator means for receiving and comparing each second adder value with a predetermined corresponding third code length sum value, and providing a corresponding second comparison value; second multiplexer means for receiving each second adder value, each corresponding third code length sum value, and each corresponding second comparison value and for providing a second multiplexer value selected from one of each second adder value and corresponding third code length sum value in accordance with said second comparison value; second register means for receiving and storing in a predetermined order each second comparison value; third adder means for receiving and adding said second multiplexer values, and providing a third adder value; third comparator means for receiving and comparing said third adder value with said fourth code length sum value, and providing a corresponding third comparison value; third register means for receiving and storing said third comparison value; third multiplexer means for receiving each of said 2×2 DCT coefficient value sub-blocks, said 4×4 DCT coefficient value sub-blocks and a corresponding predetermined one of said first register means stored first comparison values, and for providing a third multiplexer value selected from one of groups of said 2×2 DCT coefficient value sub-blocks and a corresponding one of said 4×4 DCT coefficient value sub-blocks in accordance with said stored corresponding first comparison value; fourth multiplexer means for receiving each third multiplexer value, said 8×8 DCT coefficient value sub-blocks and a corresponding predetermined one of said second register means stored second comparison values, and for providing a fourth multiplexer value selected from one each third multiplexer value and a corresponding one of said 8×8 DCT coefficient value sub-blocks in accordance with said stored corresponding second comparison value; fifth multiplexer means for receiving each fourth multiplexer value, said 16×16 DCT coefficient value block and a corresponding predetermined one of said third register means stored third comparison values, and for providing a fifth multiplexer value selected from one each fourth multiplexer value and said 16×16 DCT coefficient value block in accordance with said stored corresponding third comparison value; serializer means for receiving said fifth multiplexer value and each of said stored first, second and third comparison values, for ordering DCT coefficient values of said fifth multiplexer value in accordance with said stored first, second and third comparison values and for providing a corresponding output of serialized DCT coefficient values; encoder means for receiving and encoding said serialized DCT coefficients according to said predetermined encoding format and for providing corresponding encoder output values; and assembler means for receiving and ordering said encoder output values and said stored first, second and third comparison values according to a predetermined format, and for providing a corresponding assembler output values.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.