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Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respect 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/60
출원번호 US-0355266 (1989-05-22)
발명자 / 주소
  • Cruickshank Ancil B. (Earlysville VA) Davis Richard K. (Crozet VA)
출원인 / 주소
  • GE Fanuc Automation North America, Inc. (Charlottesville VA 02)
인용정보 피인용 횟수 : 102  인용 특허 : 0

초록 ▼

A reconfigurable counter is provided which includes first and second memories coupled via a common bus to a microprocessor which controls the process of configuring and reconfiguring the counter. A programmable hardware array, coupled to the microprocessor, is capable of being programmed to emulate

대표청구항 ▼

A reconfigurable counter comprising: a microprocessor; a bus coupled to said microprocessor; first memory means, coupled to said microprocessor by said bus, for simultaneously storing a plurality of counter configuration files which respectively define a plurality of predetermined different counters

이 특허를 인용한 특허 (102)

  1. Ho, Jae-ick, Apparatus for inputting and detecting a display data channel in manufacturing a monitor.
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  3. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
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  4. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
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  5. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
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  6. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  8. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  11. Vorbach, Martin, Data processing system.
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  12. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
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  13. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
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  14. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.
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  16. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.
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  17. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
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  18. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
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  25. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  45. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
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  46. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
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  49. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
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  50. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
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  51. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  59. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  66. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
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