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Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/76
  • H01L-021/265
출원번호 US-0401470 (1989-08-29)
발명자 / 주소
  • Mitchell Allan T. (Garland TX) Riemenschneider Bert R. (Murphy TX)
출원인 / 주소
  • Texas Instruments Incorporated (Dallas TX 02)
인용정보 피인용 횟수 : 50  인용 특허 : 0

초록 ▼

An electrically, programmable read-only memory cell is formed at a face (10) of a semiconductor layer (12). This cell comprises a doped drain region (36) and a doped source region (38) that are spaced from each other by a gate region (40). An ONO memory stack (28) is formed to extend over a portion

대표청구항 ▼

A method for manufacturing an electrically programmable read-only memory cell formed at a face of a semiconductor layer, comprising the steps: forming a first gate insulator layer over said semiconductor substrate; forming a dielectric floating gate electrode layer over said first gate insulator lay

이 특허를 인용한 특허 (50)

  1. Dadashev, Oleg; Betser, Yoram; Maayan, Eduardo, Apparatus and methods for multi-level sensing in a memory array.
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  2. Kushnarenko, Alexander, Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same.
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  3. Shappir, Assaf, Contact in planar NROM technology.
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  4. Bloom, Ilan; Eitan, Boaz; Irani, Rustom, Dense non-volatile memory array and method of fabrication.
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  5. Irani, Rustom; Eitan, Boaz; Bloom, Ilan; Shappir, Assaf, Double density NROM with nitride strips (DDNS).
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  6. Sofer,Yair; Maayan,Eduardo; Betser,Yoram, Dynamic matching of signal path and reference path for sensing.
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  7. Maayan, Eduardo; Eliyahu, Ron; Eitan, Boaz, EEPROM array and method for operation thereof.
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  8. Halliyal Arvind ; Ogle Robert B. ; Komori Hideki ; Au Kenneth, High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device.
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  9. Jeon, Joong S.; Halliyal, Arvind, Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices.
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  10. Betser, Yoram; Kushnarenko, Alexander; Dadashev, Oleg, Measuring and controlling current consumption and output current of charge pumps.
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  11. Polansky, Yan; Lavan, Avi, Memory array programming circuit and a method for using the circuit.
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  12. Willer, Josef; Polei, Veronika, Memory cell fabrication method and memory cell configuration.
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  13. Shin, Yoo-Cheol; Choi, Jeong-Hyuk; Hur, Sung-Hoi, Memory device and fabrication method thereof.
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  14. Dadashev,Oleg, Method and apparatus for measuring charge pump output current.
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  15. Maayan, Eduardo; Eitan, Boaz; Lann, Ameet, Method for programming a reference cell.
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  16. Maayan,Eduardo; Eliyahu,Ron; Lann,Ameet; Eitan,Boaz, Method for programming a reference cell.
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  17. Lusky, Eli; Eitan, Boaz, Method of erasing non-volatile memory cells.
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  18. Chen, Ming-Shang; Lu, Wen-Pin, Method of fabricating NAND-type flash EEPROMS without field oxide isolation.
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  19. Park Young-Keun,KRX, Method of fabricating flash memory cell.
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  20. Ghneim Said N. ; Fulford ; Jr. H. Jim, Method of making non-volatile memory device having a floating gate with enhanced charge retention.
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  21. Eitan, Boaz; Shainsky, Natalie, Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection.
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  22. Shappir,Assaf; Eisen,Shai, Method, circuit and systems for erasing one or more non-volatile memory cells.
    상세보기
  23. Cohen, Guy; Polansky, Yan, Method, system and circuit for programming a non-volatile memory array.
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  24. Cohen,Guy, Method, system, and circuit for operating a non-volatile memory array.
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  25. Shappir,Assaf; Avni,Dror; Eitan,Boaz, Method, system, and circuit for operating a non-volatile memory array.
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  26. Eitan, Boaz; Shainsky, Natalie, NROM non-volatile memory and mode of operation.
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  27. Eitan,Boaz, Non-volatile memory cell and non-volatile memory devices.
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  28. Maayan, Eduardo, Non-volatile memory device and method for reading cells.
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  29. Ghneim Said N. ; Fulford ; Jr. H. Jim, Non-volatile memory device having a floating gate with enhanced charge retention.
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  30. Lusky, Eli; Shappir, Assaf; Irani, Rustom; Eitan, Boaz, Non-volatile memory structure and method of fabrication.
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  31. Lusky,Eli; Eitan,Boaz; Cohen,Guy; Maayan,Eduardo, Operating array cells with matched reference cells.
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  32. Shappir,Assaf; Eisen,Shai, Partial erase verify.
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  33. Jeon, Joong, Preparation of composite high-K / standard-K dielectrics for semiconductor devices.
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  35. Halliyal, Arvind; Jeon, Joong S.; Ngo, Minh Van; Ogle, Robert B., Preparation of composite high-K/standard-K dielectrics for semiconductor devices.
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  36. Halliyal, Arvind; Jeon, Joong S.; Ngo, Minh Van; Ogle, Robert B., Preparation of composite high-K/standard-K dielectrics for semiconductor devices.
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  37. Dawn M. Hopper ; David K. Foote ; Bharath Rangarajan ; Arvind Halliyal, Process for fabricating an ONO structure having a silicon-rich silicon nitride layer.
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  38. Lusky,Eli; Bloom,Ilan; Shappir,Assaf; Eitan,Boaz, Protection of NROM devices from charge damage.
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  39. Bloom, Iian; Eitan, Boaz, Protective layer in memory device and method therefor.
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  40. Bloom,Ilan; Ettan,Boaz, Protective layer in memory device and method therefor.
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  41. Eitan, Boaz, Secondary injection for NROM.
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  42. Kim, Dong-Jun; Kim, Jin-Ho; Lee, Yong-Kyu; Cho, Min-Soo; Ryu, Eui-Youl, Semiconductor device having a flash memory cell and fabrication method thereof.
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  43. Kim, Dong-Jun; Kim, Jin-Ho; Lee, Yong-Kyu; Cho, Min-Soo; Ryu, Eui-Youl, Semiconductor device having a flash memory cell and fabrication method thereof.
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  44. Yano,Kazuo; Ishii,Tomoyuki; Hashimoto,Takashi; Seki,Koichi; Aoki,Masakazu; Sakata,Takeshi; Nakagome,Yoshinobu; Takeuchi,Kan, Semiconductor element and semiconductor memory device using the same.
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  45. Ngo,Minh Van; Halliyal,Arvind; Kamal,Tazrien; Shiraiwa,Hidehiko; Sugino,Rinji; Hopper,Dawn; Gao,Pei Yuan, Semiconductor memory with data retention liner.
    상세보기
  46. Eitan,Boaz, Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping.
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  47. Wang, Zhigang; Guo, Xin; He, Yue-Song, Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling.
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  48. Halliyal, Arvind; Ramsbey, Mark T.; Chang, Kuo-Tung; Tripsas, Nicholas H.; Ogle, Robert B., Use of high-K dielectric material in modified ONO structure for semiconductor devices.
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  49. Halliyal, Arvind; Ramsbey, Mark T.; Zhang, Wei; Randolph, Mark W.; Cheung, Fred T. K., Use of high-K dielectric material in modified ONO structure for semiconductor devices.
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  50. Halliyal, Arvind; Ramsbey, Mark T.; Chang, Kuo-Tung; Tripsas, Nicholas H.; Ogle, Robert B., Use of high-k dielectric materials in modified ONO structure for semiconductor devices.
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