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Dielectric medium for capacitor of semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/02
  • H01L-029/04
출원번호 US-0637314 (1991-01-03)
우선권정보 KR-0009966 (1990-07-02)
발명자 / 주소
  • Lee Sangin (Suwon KRX)
출원인 / 주소
  • Samsung Electronics Co., Ltd. (Kwonseon KRX 03)
인용정보 피인용 횟수 : 74  인용 특허 : 0

초록 ▼

A dielectric medium for the capacitor of a semiconductor device is disclosed. The dielectric material is prepared by replacing Sr and Ba in (Sr, Ba)Nb2O6 with La, and the replacement is carried out by adding 2 mole % or more of La2O3 to (Sr,Ba)Nb2O6, thereby forming a composition (SrxBa1-x)1-(3/2)yL

대표청구항

A dielectric medium for the capacitor of semiconductor device, comprising a composition of (SrxBa1-x)1-(3/2)yLayNb2O6(0.25≤x≤0.5, 0.04≤y).

이 특허를 인용한 특허 (74)

  1. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
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  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
    상세보기
  3. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
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  4. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
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  5. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
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  6. Fujii, Shohei; Masaoka, Raitarou; Uchiyama, Hiroki; Shirokawa, Maiko, Dielectric composition and electronic component.
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  7. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
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  8. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
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  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  17. Shaheen,Mohamad A.; Doyle,Brian; Dutta,Suman; Chau,Robert S.; Tolchinsky,Peter, High mobility tri-gate devices and methods of fabrication.
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  18. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
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  19. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
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  20. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
    상세보기
  21. Shinichiro Hayashi JP; Vikram Joshi ; Narayan Solayappan ; Joseph D. Cuchiaro ; Carlos A. Paz de Araujo, Interlayer oxide containing thin films for high dielectric constant application.
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  22. Hayashi, Shinichiro; Joshi, Vikram; Solayappan, Narayan; Cuchiaro, Joseph D.; Paz de Araujo, Carlos A., Interlayer oxide containing thin films for high dielectric constant application of the formula AB2O6 or AB2O7.
    상세보기
  23. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
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  24. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  25. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  26. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  27. Hayashi, Shinichiro; Joshi, Vikram; Solayappan, Narayan; Cuchiaro, Joseph D.; Paz de Araujo, Carlos A., Method for forming an integrated circuit.
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  28. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
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  29. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
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  30. Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
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  31. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
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  32. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
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  33. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
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  34. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
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  35. Doyle, Brian S.; Datta, Suman; Jin, Been Yih; Chau, Robert, Non-planar MOS structure with a strained channel region.
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  36. Doyle,Brian S.; Datta,Suman; Jin,Been Yih; Chau,Robert, Non-planar MOS structure with a strained channel region.
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  37. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
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  38. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
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  39. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  40. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  41. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  42. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  43. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  44. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  45. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  46. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  47. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  48. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  49. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
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  50. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
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  51. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
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  52. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
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  53. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
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  54. Cuchiaro Joseph D. ; Joshi Vikram ; DaCruz Claudia P. ; McNelis John M. ; Paz de Araujo Carlos A., Process for making an integrated circuit with high dielectric constant barium-strontium-niobium oxide.
    상세보기
  55. Kwon Hong KR; Yong-Sik Yu KR, Semiconductor device having a ferroelectric capacitor and method for the manufacture thereof.
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  56. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
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  57. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
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  58. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
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  59. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
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  60. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
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  61. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  62. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  63. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  64. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  65. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  66. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman, Tri-gate devices and methods of fabrication.
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  67. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
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  68. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
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  69. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
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  70. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
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  71. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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  72. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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  73. Chau,Robert; Datta,Suman; Doyle,Brian S; Jin,Been Yih, Tri-gate transistors and methods to fabricate same.
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  74. Shaheen, Mohamad A.; Rachmady, Willy; Tolchinsky, Peter, Ultra-thin oxide bonding for S1 to S1 dual orientation bonding.
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