[특허]High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and mu

High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and mu 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/22
출원번호	US-0211977 (1988-06-27)
발명자 / 주소	Beckwith Robert F. (Framingham MA) Johnson Neil J. (Burlington MA) Irukulla Suren (Holliston MA) Schwartz Steven (Sudbury MA) Mohapatra Nihar (Milford MA)
출원인 / 주소	Prime Computer, Inc. (Framingham MA 02)
인용정보	피인용 횟수 : 112 인용 특허 : 0

초록 ▼

A pipelined central processor capable of executing both single-cycle instructions and multicycle instructions is provided. An instruction fetch stage of the processor includes an instruction cache memory and a prediction cache memory that are commonly addressed by a program counter register. The instruction cache memory stores instructions of a program being executed and microinstructions of a multicycle instruction interpreter. The prediction cache memory stores interpreter call predictions and interpreter entry addresses at the addresses of the multicycle intructions. When a call prediction occurs, the entry address of the instruction interpreter is loaded into the program counter register on the processing cycle immediately following the call prediction, and a return address is pushed onto a stack. The microinstructions of the interpreter are fetched sequentially from the instruction cache memory. When the interpreter is completed, the prediction cache memory makes a return prediction. The return address is transferred from the stack to the program counter register on the processing cycle immediately following the return prediction, and normal program flow is resumed. The prediction cache memory also stores branch instruction predictions and branch target addresses.

대표청구항 ▼

Digital processing apparatus for executing stored program instructions including single-cycle instructions and multicycle instructions during multiple processing cycles, comprising: instruction memory means for providing said program instructions in response to program addresses and for providing microinstructions of a multicycle instruction interpreter in response to microinstruction addresses; prediction means responsive to different ones of said program addresses for making predictions of multicycle instructions and predictions of single cycle instructions, said predictions of multicycle instructions including predictions of calls to said instruction interpreter and predictions of returns from said instruction interpreter, said prediction means including a cache memory for storage and readout of said call predictions and instruction interpreter entry addresses respectively associated with each of said call predictions, each of said call predictions and said entry addresses being stored at an address corresponding to the program address for which the call prediction is made, and for storage and readout of each of said return predictions at an address corresponding to the microinstruction address for which the return prediction is made; control means for providing successive program addresses to said instruction memory means for accessing said program instructions in response to predictions of single-cycle instructions and for providing successive microinstruction addresses to said instruction memory means in response to each prediction of a multicycle instruction until completion of the multicycle instruction interpreter, said control means including program counter means for holding a current address for accessing said instruction memory means on each processing cycle and for incrementing the current address on successive processing cycles, stack memory means coupled to said program counter means, control logic means responsive to each of said call predictions for loading a return program address from said program counter means into said stack memory means, and selector means responsive to each of said call predictions for loading the entry address into said program counter means and responsive to each of said return predictions for transferring said return program address from said stack memory means to said program counter means; means responsive to said program instructions and said microinstructions provided by said instruction memory means for executing said program instructions and said microinstructions; and means for validating said predictions and for updating said prediction means when said predictions are incorrect.

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연합인증

High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and mu 원문보기

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연합인증

High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and mu 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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이 특허를 인용한 특허 (112)

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