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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0608415 (1990-11-02) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 309 인용 특허 : 0 |
A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four near
A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.
A programmable logic array comprising: a plurality of logic cells, wherein each cell except those at the edges of the array has four nearest-neighbor cells, one to the left (or West), one to the right (or East), one above (or to the North) and one below (or to the South) so as to form an array in wh
A programmable logic array comprising: a plurality of logic cells, wherein each cell except those at the edges of the array has four nearest-neighbor cells, one to the left (or West), one to the right (or East), one above (or to the North) and one below (or to the South) so as to form an array in which said logic cells are aligned in rows and columns, each cell comprising: eight inputs, two from each of its four nearest neighbors, eight outputs, two to each of its four nearest neighbors, means for storing a plurality of control bits, means for multiplexing the eight inputs onto first and second input leads, the inputs connected to said input leads being specified by control bits stored in said storing means, and logic means for generating signals on said outputs in response to signals on said input leads and control bits stored in said storing means.
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