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Method of manufacturing semiconductor device by controlling the profile of the density of p-type impurities in the sourc 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/22
  • H01L-021/266
출원번호 US-0666912 (1991-03-11)
우선권정보 JP-0061531 (1990-03-13)
발명자 / 주소
  • Sakagami Eiji (Kawasaki JPX)
출원인 / 주소
  • Kabushiki Kaisha Toshiba (Kawasaki JPX 03)
인용정보 피인용 횟수 : 35  인용 특허 : 0

초록

The invention provides a novel method of manufacturing a semiconductor device comprising those sequential steps including the following, formation of a floating gate electrode on a region predetermined for the formation of the first conductive channel across an insulation film, followed by superimpo

대표청구항

A method of manufacturing a semiconductor device, comprising the steps of: forming a semiconductor element region on a semiconductor substrate; forming a first insulation layer on a resulting semiconductor structure; forming a first conductive layer on said first insulation layer; forming a second i

이 특허를 인용한 특허 (35)

  1. Ho Simon Chan Tze,SGX ; Stodart Tyrone Philip,SGX ; Kim Sung Rae,SGX ; Lin Yung-Tao,SGX, Flash memory cell structure with improved channel punch-through characteristics.
  2. Hsu Ching-Hsiang,TWX ; Liang Mong-Song,TWX ; Chung Steve S.,TWX, Highly reliable flash memory structure with halo source.
  3. Buxo Juan ; Dow Diann ; Ilderem Vida ; Zhou Ziye ; Zirkle Thomas E., Insulated gate field effect transistor structure having a unilateral source extension.
  4. Song, Seung-Hyun; Lee, Seung-Chul; Jang, In-Kook, Integrated circuit device with transistors having different threshold voltages.
  5. Anjum Mohammed (Austin TX) Koop Klaus H. (Elgin TX) Kyaw Maung H. (Austin TX), Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices.
  6. He, Yue-Song; Fastow, Richard; Guo, Xin, Method and system for improving short channel effect on a floating gate device.
  7. Thurgate Timothy J. ; Chan Vei-Han, Method and system for providing a drain side pocket implant.
  8. Enomoto Shuichi (Tokyo JPX), Method for manufacturing a semiconductor integrated circuit device having a stack gate structure.
  9. Ueda Naoki,JPX ; Tanaka Kenichi,JPX ; Tanaka Masaaki,JPX, Method of fabricating EEPROM using oblique implantation.
  10. Akram Salman ; Ditali Akram, Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor.
  11. Akram Salman ; Ditali Akram, Method of forming a multiple inplant lightly doped drain (MILDD) field effect transistor.
  12. Hsu, Sheng Teng; Li, Tingkai; Zhang, Fengyan, Method of making a self-aligned ferroelectric memory transistor.
  13. Tani Tomofune (Tokyo JPX), Method of making an isolation layer stack semiconductor device.
  14. Ghneim Said N. ; Fulford ; Jr. H. Jim, Method of making non-volatile memory device having a floating gate with enhanced charge retention.
  15. Fukimoto Takahiro,JPX, Method of manufacturing EPROM device.
  16. Yim, Yong-Sik; Choi, Jung-Dal, NAND-type flash memory device and method of forming the same.
  17. Yim, Yong-Sik; Choi, Jung-Dal, Nand-type flash memory device and method of forming the same.
  18. Luning Scott D. ; Randolph Mark, Non-self-aligned side channel implants for flash memory cells.
  19. Ghneim Said N. ; Fulford ; Jr. H. Jim, Non-volatile memory device having a floating gate with enhanced charge retention.
  20. Woodbury Dustin Alexander ; Beasom James Douglas ; Swonger James Winthrop, P-collector H.V. PMOS switch VT adjusted source/drain.
  21. Yan, Feng; Zhang, Rong; Shi, Yi; Pu, Lin; Xu, Yue; Wu, Fuwei; Bo, Xiaofeng; Xia, Haoguang, Photosensitive detector with composite dielectric gate MOSFET structure and its signal readout method.
  22. Kumashiro Shigetaka,JPX ; Takeuchi Kiyoshi,JPX, Reverse profiling method for profiling modulated impurity density distribution of semiconductor device.
  23. Fukumoto Takahiro,JPX, Semiconductor memory device and method of manufacturing the same.
  24. Kawaguchi Tsutomu,JPX ; Katada Mitsutaka,JPX, Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate.
  25. Nakao Hironobu,JPX, Semiconductor memory device with three-dimensional cluster distribution.
  26. Ahmad Aftab ; Prall Kirk, Semiconductor processing method of fabricating field effect transistors.
  27. Ahmad Aftab ; Prall Kirk, Semiconductor processing method of fabricating field effect transistors.
  28. Ahmad Aftab ; Prall Kirk, Semiconductor processing method of fabricating field effect transistors.
  29. Aftab Ahmad ; David J. Keller, Semiconductor transistor devices and methods for forming semiconductor transistor devices.
  30. Ahmad Aftab ; Keller David J., Semiconductor transistor devices and methods for forming semiconductor transistor devices.
  31. Ahmad Aftab ; Keller David J., Semiconductor transistor devices and methods for forming semiconductor transistor devices.
  32. Ahmad Aftab ; Keller David J., Semiconductor transistor devices and methods for forming semiconductor transistor devices.
  33. Ahmad, Aftab; Keller, David J., Semiconductor transistor devices and structures with halo regions.
  34. He, Yue-song; Haddad, Sameer; Thurgate, Timothy; Chang, Chi, Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory.
  35. Choi Jeong Yeol ; Chien Chung-Jen ; Han Chung Chyung ; Lien Chuen-Der, Structure for controlling threshold voltage of MOSFET.
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