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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0673020 (1991-03-21) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 664 인용 특허 : 0 |
A semiconductor chip having contacts on the periphery of its top surface is provided with an interposer overlying the central portion of the top surface. Peripheral contact leads extend inwardly from the peripheral contacts to central terminals on the interposer. The terminals on the interposer may
A semiconductor chip having contacts on the periphery of its top surface is provided with an interposer overlying the central portion of the top surface. Peripheral contact leads extend inwardly from the peripheral contacts to central terminals on the interposer. The terminals on the interposer may be connected to a substrate using techniques commonly employed in surface mounting of electrical devices, such as solder bonding. The leads, and preferably the interposer, are flexible so that the terminals are movable with respect to the contacts on the chip, to compensate for differential thermal expansion of the chip and substrate. The terminals on the interposer may be disposed in an area array having terminals disposed at substantially equal spacings throughout the area of the interposer, thus providing substantial distances between the terminals while accommodating all of the terminals in an area approximately the same size as the area of the chip itself. The interposer may be provided with a compliant layer disposed between the terminals and the chip to permit slight vertical movement of the terminals towards the chip during testing operations. The chip and interposer assembly may be electrically tested prior to assembly to the substrate. A compliant layer disposed between the terminals and the chip permits slight vertical movement of the terminals towards the chip during testing operations, in which the terminals on the interposer are engaged with an assembly of test probles. The entire assembly is compact.
A semiconductor chip assembly comprising: (a) a semiconductor chip having a front surface defining the top of the chip, said front surface including a central region and a peripheral region surrounding said central region, whereby said central region is disposed inwardly of said peripheral region, s
A semiconductor chip assembly comprising: (a) a semiconductor chip having a front surface defining the top of the chip, said front surface including a central region and a peripheral region surrounding said central region, whereby said central region is disposed inwardly of said peripheral region, said chip having a plurality of peripheral contacts disposed in said peripheral region of said front surface; (b) a sheetlike dielectric interposer overlying said central region of said chip front surface, said interposer having a first surface facing toward said chip and a second surface facing away from said chip, said interposer having outward edges disposed inwardly of said peripheral contacts; (c) a plurality of central terminals disposed on said interposer and overlying said central region of said chip front surface, said central terminals facing away from said chip and being exposed at said second surface of said interposer for interconnection to a substrate; and (d) a plurality of peripheral contact leads connecting at least some of said peripheral contacts and at lest some of said central terminals, each said peripheral contact lead having a central terminal end overlying said interposer and connected to one of said central terminals and a contact end projecting outwardly beyond one of said edges of said interposer and connected to one of said peripheral contacts, whereby each said peripheral contact lead extends inwardly from one of said peripheral contacts to one of said central terminals on said interposer, said central terminals being movable with respect to said contacts so as to compensate for thermal expansion of said chip.
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