[특허]State controlled instruction logic management apparatus included in a pipelined processing unit

State controlled instruction logic management apparatus included in a pipelined processing unit 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/30 G06F-009/38
출원번호	US-0374881 (1989-06-30)
발명자 / 주소	Staplin Deborah K. (Chelmsford MA) Shen Jian-Kuo (Belmont MA)
출원인 / 주소	Bull HN Information Systems Inc. (Billerica MA 02)
인용정보	피인용 횟수 : 15 인용 특허 : 0

초록 ▼

A pipelined processing unit which includes an instruction unit stage containing logic management apparatus for processing a set of complex instructions. The logic management apparatus includes state control circuits which produce a series or sequence of control states used in tracking the different types of instructions of the complex instruction set being processed. Different ones of the states are used for different types of instructions so as to enable the different pipeline stages to operate both independently and jointly to complete the execution of different instructions of the complex instruction set.

대표청구항 ▼

Instruction apparatus for controlling the execution of a plurality of different types of instructions of an instruction set in a pipelined mode by a plurality of serially coupled stages of a pipelined processing unit, each stage for performing a different operation in the execution of each instruction received by said processing unit, said instructions being received by a first one of said stage, in succession, and said apparatus being included in a first one of said stages and comprising: (a) crack decode means for generating a plurality of signals in response to each instruction of said instruction set, said plurality of signals differing for each different type of instruction; (b) control state means coupled to said crack decode means for generating a plurality of state signals corresponding to a number of machine states in response to different ones of said plurality of signals, said state signals generated by said control state means being determined in part by said plurality of signals and each one of said state signals generated defining a current machine state of said control state means; and, (c) means for applying said state signals to one or both of said first stage and a second one of said pipeline stages for causing said stages to execute different operations for each instructions causing the generation of a corresponding one of said state signals.

이 특허를 인용한 특허 (15)

Alexander, Khary J.; Busaba, Fadi; Curran, Brian; Giamei, Bruce; Jacobi, Christian, Cracking destructively overlapping operands in variable length instructions.
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Busaba, Fadi; Curran, Brian; Eisen, Lee; Jacobi, Christian; Schroter, David A.; Schwarz, Eric, Dual issuing of complex instruction set instructions.
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Alexander, Khary J.; Busaba, Fadi; Curran, Brian; Giamei, Bruce; Jacobi, Christian; Mitchell, James R., History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties.
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Busaba, Fadi; Curran, Brian; Eisen, Lee; Giamei, Bruce; Hutton, David, Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits.
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Busaba, Fadi; Giamei, Bruce; Hutton, David; Schwarz, Eric, Instruction cracking based on machine state.
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Busaba, Fadi; Curran, Brian; Giamei, Bruce; Jacobi, Christian; Li, Wen, Instruction length based cracking for instruction of variable length storage operands.
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Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring efficiency of branch unit operation in a processing system.
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Levine Frank Eliot (Austin TX) Roth Charles Philip (Austin TX) Welbon Edward Hugh (Austin TX), Method and system for performance monitoring of dispatch unit efficiency in a processing system.
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Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring of misaligned memory accesses in a processing system.
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Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring through identification of frequency and length of time of execution of ser.
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Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring time lengths of disabled interrupts in a processing system.
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Witt David B., Microprocessor with dynamically extendable pipeline stages and a classifying circuit.
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Ando Hideki,JPX, Pipelining device in a parallel processing apparatus and an instruction supplying method therefor.
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Huynh Dieu ; Leung Wan L., Special instruction register including allocation field utilized for temporary designation of physical registers as general registers.
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Blomgren James S. ; Brashears Cheryl Senter, Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
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State controlled instruction logic management apparatus included in a pipelined processing unit 원문보기

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State controlled instruction logic management apparatus included in a pipelined processing unit 원문보기

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이 특허를 인용한 특허 (15)

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