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Programmable logic cell and array

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0705243 (1991-05-24)
발명자 / 주소
  • Furtek Frederick C. (Arlington MA)
출원인 / 주소
  • Concurrent Logic, Inc. (Sunnyvale CA 02) Apple Computer (Cupertino CA 02)
인용정보 피인용 횟수 : 29  인용 특허 : 0

초록

A logic cell is described having four inputs, four outputs, a control store, means for multiplexing the four inputs onto two leads and logic means that operate in response to the signals on the two leads and signals from the control store to produce output signals which are applied to the four outpu

대표청구항

A two-dimensional array of logic cells, each cell except those at the edges of the array having four nearest neighbors, one to the left (or West), one to the right (or East), one above (or to the North) and one below (or to the South), each cell comprising: four inputs, one from each of its four nea

이 특허를 인용한 특허 (29)

  1. Redgrave, Jason; Schmit, Herman, Barrel shifter implemented on a configurable integrated circuit.
  2. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configurable routing resources that have asymmetric input and/or outputs.
  3. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs.
  4. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with logic resources with offset connections.
  5. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with routing circuits with offset connections.
  6. Teig, Steven; Redgrave, Jason, Configurable IC's with dual carry chains.
  7. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.
  8. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.
  9. Schmit,Herman; Teig,Steven; Hutchings,Brad, Configurable integrated circuit with parallel non-neighboring offset connections.
  10. Gallup Michael G. (Austin TX) Goke L. R. (Austin TX) Seaton ; Jr. Robert W. (Austin TX) Lawell Terry G. (Austin TX), Data processing system and method thereof.
  11. Gallup Michael G. ; Goke L. Rodney, Data processing system and method thereof.
  12. Gallup Michael G. ; Goke L. Rodney ; Seaton ; Jr. Robert W. ; Lawell Terry G. ; Osborn Stephen G. ; Tomazin Thomas J., Data processing system and method thereof.
  13. Gallup Michael G. ; Goke L. Rodney ; Seaton ; Jr. Robert W. ; Lawell Terry G. ; Osborn Stephen G. ; Tomazin Thomas J., Data processing system and method thereof.
  14. Gallup Michael G. (Austin TX) Goke L. Rodney (Austin TX) Seaton ; Jr. Robert W. (Austin TX), Data processor for conditionally modifying extension bits in response to data processing instruction execution.
  15. Gallup Michael G. (Austin TX) Goke L. Rodney (Austin TX) Seaton ; Jr. Robert W. (Austin TX), Data processor for performing a comparison instruction using selective enablement and wired boolean logic.
  16. Spielman Jason ; Huang Yee-Wei ; Gallup ; deceased Michael G. ; Seaton ; Jr. Robert W. ; Goke L. Rodney, Efficient stack utilization for compiling and executing nested if-else constructs in a vector data processing system.
  17. Martin, Grégorie; Cavalli, David; Firmin, Fabian, Embedded FPGA with multiple configurable flexible logic blocks instantiated and interconnected by abutment.
  18. Goetting F. Erich, FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses.
  19. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
  20. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
  21. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
  22. Gallup Michael G. ; Goke L. Rodney ; Bell Meltin, Method and apparatus for performing a vector skip instruction in a data processor.
  23. Wiles Michael F. (Round Rock TX) Bell Meltin (Austin TX) Gallup Michael G. (Austin TX) Goke L. Rodney (Austin TX) Davis Jack R. (Austin TX) Welty Erik L. (Austin TX), Method for complex data movement in a multi-processor data processing system.
  24. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  25. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  26. Bertolet Allan Robert ; Clinton Kim P.N. ; Fuller Christine Marie ; Gould Scott Whitney ; Hartman Steven Paul ; Iadanza Joseph Andrew ; Keyser Frank Ray ; Millham Eric Ernest ; Reny Timothy Shawn ; W, Programmable inverter circuit used in a programmable logic cell.
  27. Bertolet Allan Robert ; Clinton Kim P. N. ; Fuller Christine Marie ; Gould Scott Whitney ; Hartman Steven Paul ; Iadanza Joseph Andrew ; Keyser Frank Ray ; Millham Eric Ernest ; Reny Timothy Shawn ; , Programmable logic cell.
  28. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  29. Spielman Jason (Austin TX) Huang Yee-Wei (Austin TX) Gallup ; deceased Michael G. (late of Austin TX by Linda Gallup ; executor ) Seaton ; Jr. Robert W. (Austin TX) Goke L. Rodney (Austin TX), Vector move instruction in a vector data processing system and method therefor.
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