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Mutliple lamination high density interconnect process and structure employing thermoplastic adhesives having sequentiall 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/11
출원번호 US-0546963 (1990-07-02)
발명자 / 주소
  • Cole
  • Jr. Herbert S. (Scotia NY) Rose James W. (Delmar NY) Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY)
출원인 / 주소
  • General Electric Company (Schenectady NY 02)
인용정보 피인용 횟수 : 46  인용 특허 : 0

초록 ▼

A high density interconnect structure incorporating a plurality of laminated dieletric layers is fabricated using thermoplastic adhesive layers of progressively lower glass transition temperature in order to maintain the stability of the already fabricated structure during the addition of the later

대표청구항 ▼

A high density interconnect structure comprising: a plurality of semiconductor chips each having contact pads on a first surface thereof; a first layer of dielectric material bonded to said semiconductor chips, said first layer of dielectric material comprising first lower and first upper sublayers,

이 특허를 인용한 특허 (46)

  1. Geefay, Frank S.; Dutton, David T.; Bai, Qing, Attachment system incorporating a recess in a structure.
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  2. Weng, Chaofu; Wu, Yi Ting, Chip package structure and manufacturing methods thereof.
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  3. Lee, Chang-Chi; Chen, Shih-Kuang; Chang, Yuan-Ting, Chip package structure and method of manufacturing the same.
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  4. Faraci Tony ; DiStefano Thomas H. ; Smith John W., Connecting multiple microelectronic elements with lead deformation.
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  5. Tony Faraci ; Thomas H. Distefano ; John W. Smith, Connecting multiple microelectronic elements with lead deformation.
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  6. Lee, Chun-Che; Su, Yuan-Chang; Lee, Ming Chiang; Huang, Shih-Fu, Embedded component device and manufacturing methods thereof.
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  7. Su, Yuan-Chang; Huang, Shih-Fu; Lee, Ming-Chiang; Wang, Chien-Hao, Embedded component substrate and manufacturing methods thereof.
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  8. Fraivillig James, Flexible laminates and method of making the laminates.
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  9. Wojnarowski Robert John ; Gorczyca Thomas Bent ; Weaver ; Jr. Stanton Earl, High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate.
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  10. Marcinkiewicz Walter M., Integrated circuit module and method.
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  11. Chen,Kuo Tso; Kung,Chen Yueh, Integrated circuit package and method of manufacture.
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  12. You,Joong Ha, Member for semiconductor package and semiconductor package using the same, and fabrication method thereof.
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  13. Robinson Douglas S. (Ames IA) Jensen Terrence C. (Ames IA) Gray Joseph N. (Ames IA), Method of fabricating a device having a wafer with integrated processing circuits thereon.
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  14. Chua,Swee Kwang; Low,Siu Waf; Chia,Yong Poo; Eng,Meow Koon; Neo,Yong Loo; Boon,Suan Jeung; Huang,Suangwu; Zhou,Wei, Method of making multichip wafer level packages and computing systems incorporating same.
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  15. Oi,Kiyoshi; Shimizu,Noriyoshi; Horikawa,Yasuyoshi, Method of manufacturing electronic part packaging structure.
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  16. Kawata, Masaki; Ito, Yuki, Method of manufacturing resin multilayer substrate.
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  17. Sheats, James, Method of packaging and interconnection of integrated circuits.
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  18. Su, Yuan-Chang; Huang, Shih-Fu; Chen, Chia-Cheng, Package carrier, semiconductor package, and process for fabricating same.
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  19. Hu, Dyi-Chung, Package substrate with lateral communication circuitry.
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  20. Higashi, Mitsutoshi; Murayama, Kei; Sakaguchi, Hideaki; Koike, Hiroko, Semiconductor device and production method thereof.
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  21. Hsieh, Chuehan; Yang, Hung-Jen; Huang, Min-Lung, Semiconductor device package with an alignment mark.
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  22. Ding, Yi-Chuan; Chen, Chia-Ching, Semiconductor device packages including connecting elements.
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  23. Ding, Yi-Chuan; Chen, Chia-Ching, Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof.
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  24. Yang, Hung-Jen; Hsieh, Chuehan; Huang, Min-Lung, Semiconductor device packages, redistribution structures, and manufacturing methods thereof.
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  25. Chen, Chia-Ching; Ding, Yi-Chuan, Semiconductor package including a stacking element.
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  26. Su, Yuan-Chang; Huang, Shih-Fu; Chen, Chia-Cheng; Chen, Tzu-Hui; Chen, Kuang-Hsiung; Hsieh, Pao-Ming; Lee, Ming Chiang; Appelt, Bernd Karl, Semiconductor package with single sided substrate design and manufacturing methods thereof.
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  27. Su, Yuan-Chang; Huang, Shih-Fu; Chen, Chia-Cheng; Chen, Tzu-Hui; Chen, Kuang-Hsiung; Hsieh, Pao-Ming; Lee, Ming Chiang; Appelt, Bernd Karl, Semiconductor package with single sided substrate design and manufacturing methods thereof.
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  28. Su, Yuan-Chang; Huang, Shih-Fu; Chen, Chia-Cheng; Chen, Tzu-Hui; Chen, Kuang-Hsiung; Hsieh, Pao-Ming; Lee, Ming Chiang; Appelt, Bernd Karl, Semiconductor package with single sided substrate design and manufacturing methods thereof.
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  29. Chen, Chia-Ching; Ding, Yi-Chuan, Stackable semiconductor package and manufacturing method thereof.
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  30. Soane David S., Stratified composite dielectric and method of fabrication.
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  31. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high density module with integrated wafer level packages.
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  32. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high-density module with integrated wafer level packages.
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  33. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high-density module with integrated wafer level packages.
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  34. Roy, Mihir K.; Salama, Islam A.; Gurumurthy, Charavana K.; Sankman, Robert L., Through mold via polymer block package.
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  35. Roy, Mihir K.; Salama, Islam A.; Gurumurthy, Charavana K.; Sankman, Robert L., Through mold via polymer block package.
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  36. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  37. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  39. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  43. Hunt, John Richard, Wafer level semiconductor package and manufacturing methods thereof.
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  44. Hunt, John Richard, Wafer level semiconductor package and manufacturing methods thereof.
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  45. Chiu, Chi-Tsung; Liao, Kuo-Hsien; Yih, Wei-Chi; Chen, Yu-Chi; Fan, Chen-Chuan, Wafer-level semiconductor device packages with electromagnetic interference shielding.
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  46. Lee, Ming-Chiang; Wang, Chien-Hao, Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof.
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