이 특허를 인용한 특허 (58)

1. Worrell Frank, Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended.

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2. Matsunami Naoto,JPX ; Yoshida Minoru,JPX ; Miyazawa Shoichi,JPX ; Oeda Takashi,JPX ; Honda Kiyoshi,JPX ; Ohno Shuji,JPX, Array disk controller for grouping host commands into a single virtual host command.

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3. Hotta Takashi (Hitachi JPX) Nakatsuka Yasuhiro (Hitachi JPX) Tanaka Shigeya (Hitachi JPX) Yamada Hiromichi (Hitachi JPX) Maejima Hideo (Hitachi JPX), Computer having a parallel operating capability.

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4. Yoav Lavi IL; Amnon Rom IL; Robert Knuth DE; Rivka Blum IL; Meny Yanni IL; Haim Granot IL; Anat Hershko IL; Georgiy Shenderovitch IL; Elliot Cohen IL; Eran Weingatren IL, Configurable long instruction word architecture and instruction set.

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5. Airaud, Cedric Denis Robert; Scalabrino, Luca; Arsanto, Frederic Jean Denis; Schon, Guillaume; Piry, Frederic Claude Marie; Tonnerre, Albin Pierick, Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit.

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6. Masahito Matsuo JP, Data processor.

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7. Park Heonchul ; Song Seungyoon Peter, Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor.

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8. Pechanek Gerald G. ; Larsen Larry D. ; Glossner Clair John ; Vassiliaadis Stamatis,NLX, Distributed processing array with component processors performing customized interpretation of instructions.

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9. Djafarian, Karim; Laurenti, Gilbert; Catan, Herve; Gillet, Vincent, Dual access instruction and compound memory access instruction with compatible address fields.

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10. Ganapathy,Kumar; Kanapathipillai,Ruban, Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations.

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11. Ganapathy, Kumar; Kanapathipillai, Ruban, Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder.

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12. Ganapathy, Kumar; Kanapathipillai, Ruban, Dyadic DSP instructions for digital signal processors.

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13. Ganapathy, Kumar; Kanapathipillai, Ruban, Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions.

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14. Miller Paul K., Embedding two different instruction sets within a single long instruction word using predecode bits.

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15. Fleck Rod G. ; Moller Ole H.,DKX ; Baror Gigy,ILX, Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline.

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16. Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.; Moreno, Jaime H.; Nair, Ravi; Prener, Daniel A., Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry.

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17. Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.; Moreno, Jaime H.; Nair, Ravi; Prener, Daniel A., Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry.

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18. Hsu, R-Ming, Instruction folding mechanism, method for performing the same and pixel processing system employing the same.

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19. Hsu,R ming, Instruction folding mechanism, method for performing the same and pixel processing system employing the same.

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20. Lin, Shuaibin, Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions.

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21. Patel, Mukesh K., Java hardware accelerator using microcode engine.

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22. Patel,Mukesh K., Java hardware accelerator using microcode engine.

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23. Patel, Mukesh K.; Raval, Udaykumar R.; Vyas, Harihar J., Java hardware accelerator using thread manager.

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24. Patel Mukesh K. ; Kamdar Jay ; Ranganath V. R., Java virtual machine hardware for RISC and CISC processors.

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25. Patel, Mukesh K; Kamdar, Jay; Ranganath, Veeraganti R., Java virtual machine hardware for RISC and CISC processors.

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26. Patel,Mukesh K.; Kamdar,Jay; Ranganath,V. R., Java virtual machine hardware for RISC and CISC processors.

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27. Resnick, David, Memories and methods for performing vector atomic memory operations with mask control and variable data length and data unit size.

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28. Resnick, David, Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same.

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29. Resnick, David, Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same.

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30. Resnick, David, Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same.

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31. Resnick, David, Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same.

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32. Resnick, David, Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same.

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33. Resnick, David, Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same.

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34. Resnick, David, Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same.

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35. Ban, Oliver Keren; Keng, Neo Hock; Tan, Wo Heem, Method and apparatus for performing out of order instruction folding and retirement.

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36. Gschwind, Michael; Sinharoy, Balaram, Method and apparatus for the dynamic identification and merging of instructions for execution on a wide datapath.

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37. Dickol John Edward ; Drerup Bernard Charles, Method and system for executing a non-native mode-sensitive instruction within a computer system.

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38. Kahle James Allan ; Kau Chin-Cheng, Method and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing par.

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39. Black Bryan (Austin TX) Denman Marvin A. (Austin TX) Eisen Lee E. (Austin TX) Golla Robert T. (Austin TX) Loper ; Jr. Albert J. (Cedar Park TX) Mallick Soummya (Austin TX) Reininger Russell A. (Austi, Method and system for recoding noneffective instructions within a data processing system.

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40. Li Stephen (Hsiao Yi) ; Song James (Sang-Won) ; Look Paul M., Method for left/right channel self-alignment.

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41. Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.; Nair, Ravi, Predication in a vector processor.

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42. Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.; Nair, Ravi, Predication in a vector processor.

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43. Gschwind, Michael K; Salapura, Valentina, Prefix computer instruction for compatibily extending instruction functionality.

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44. Gschwind, Michael K; Salapura, Valentina, Prefix computer instruction for compatibly extending instruction functionality.

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45. Djafarian, Karim; Laurenti, Gilbert; Gillet, Vincent, Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution.

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46. Gschwind, Michael K.; Salapura, Valentina, Scalable decode-time instruction sequence optimization of dependent instructions.

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47. VanDyke John Paul ; Sangsland Irving, Self-propelled independent mechanical handling device.

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48. DeLano Eric R. (Fort Collins CO), System and method for selecting and buffering even and odd instructions for simultaneous execution in a computer.

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49. Vassiliadis Stamatis ; Blaner Bartholomew, System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compou.

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50. Le Hung Qui, System for pairing dependent instructions having non-contiguous addresses during dispatch.

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51. Gschwind, Michael K.; Salapura, Valentina, Using register last use infomation to perform decode-time computer instruction optimization.

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52. Gschwind, Michael K; Salapura, Valentina, Using register last use information to perform decode time computer instruction optimization.

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53. Abiko, Shigeshi; Laurenti, Gilbert; Buser, Mark; Ponsot, Eric, Various length software breakpoint in a delay slot.

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54. Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.; Nair, Ravi; Prener, Daniel A., Vector processing in an active memory device.

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55. Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.; Nair, Ravi; Prener, Daniel A., Vector processing in an active memory device.

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56. Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.; Nair, Ravi, Vector register file.

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57. Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.; Nair, Ravi, Vector register file.

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58. Patel, Mukesh K., Virtual machine hardware for RISC and CISC processors.

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