[특허]Parallel processing system with processor array and network communications system for transmitting messages of variable

Parallel processing system with processor array and network communications system for transmitting messages of variable 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/00 G06F-015/80
출원번호	US-0943375 (1986-12-17)
발명자 / 주소	Gifford David K. (Cambridge MA)
출원인 / 주소	Massachusetts Institute of Technology (Cambridge MA 02)
인용정보	피인용 횟수 : 94 인용 특허 : 0

초록 ▼

A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruction. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.

대표청구항 ▼

A parallel processing array including a plurality of processing elements and an interconnection network for transferring messages among the processing elements, each processing element including network interface means and means for generating a message in the form of one or more blocks, said message including a destination address field, said network interface means including: A. a plurality of receive circuit means each connected to receive message blocks from a transmit circuit means of a connected processing element; B. a plurality of transmit circuit means each connected to transmit message blocks to a receive circuit means of a connected processing element; C. transfer means for coupling the message blocks from any one of said receive circuit means to any one of said transmit circuit means in response to the contents of a destination address field, comprising: i. switch means for controllably coupling the message blocks received in any one of said receive circuit means to any one of said transmit circuit means, ii. routing circuit control means connected to said switch means and to each of said receive circuit means, including means for (a) storing a correspondence between a destination address and one of said transmit circuit means, (b) reading the destination address field from a message, (c) identifying, in response to the destination address field of said message, a corresponding one of said transmit circuit means, and then enabling said switch means to couple all blocks of said message thereafter received by any of said receive circuit means to said corresponding one of said transmit circuit means, and (d) when the last block of said message is received by one of said receive circuit means, disabling said switch means after said last block is coupled to said corresponding one of said transmit circuit means.

이 특허를 인용한 특허 (94)

Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Kuchinski David Christopher ; Knowles Billy Jack ; Nier Richard Edward ; Retter Eric Eugene ; Richardson Robert Reist ; Rolfe, APAP I/O programmable router.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Parallel processing system with processor array and network communications system for transmitting messages of variable 원문보기

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Parallel processing system with processor array and network communications system for transmitting messages of variable 원문보기

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